[PATCH 2/2] drm/amdgpu/gfx10: move update_spm_vmid() out of rlc_init()

[Alex Deucher]

rlc_init() is part of sw_init() so it should not touch hardware.
Additionally, calling the rlc update_spm_vmid() callback
directly invokes a gfx on/off cycle which could result in
powergating being enabled before hw init is complete.  Split
update_spm_vmid() into an internal implementation for local
use without gfxoff interaction and then the rlc callback
which includes gfxoff handling.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 91261ed489257..1b188aeba6515 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3506,6 +3506,8 @@ static void gfx_v10_3_set_power_brake_sequence(struct 
amdgpu_device *adev);
 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
                                           uint16_t pasid, uint32_t flush_type,
                                           bool all_hub, uint8_t dst_sel);
+static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
+                                              unsigned vmid);
 
 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t 
queue_mask)
 {
@@ -4187,11 +4189,6 @@ static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
                        return r;
        }
 
-       /* init spm vmid with 0xf */
-       if (adev->gfx.rlc.funcs->update_spm_vmid)
-               adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
-
-
        return 0;
 }
 
@@ -5169,6 +5166,8 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device 
*adev)
 
                gfx_v10_0_init_csb(adev);
 
+               gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
+
                if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
                        gfx_v10_0_rlc_enable_srm(adev);
        } else {
@@ -5199,6 +5198,8 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device 
*adev)
 
                gfx_v10_0_init_csb(adev);
 
+               gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
+
                adev->gfx.rlc.funcs->start(adev);
 
                if (adev->firmware.load_type == 
AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
@@ -5207,6 +5208,7 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device 
*adev)
                                return r;
                }
        }
+
        return 0;
 }
 
@@ -7907,12 +7909,11 @@ static int gfx_v10_0_update_gfx_clock_gating(struct 
amdgpu_device *adev,
        return 0;
 }
 
-static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned 
vmid)
+static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
+                                              unsigned vmid)
 {
        u32 reg, data;
 
-       amdgpu_gfx_off_ctrl(adev, false);
-
        /* not for *_SOC15 */
        reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
        if (amdgpu_sriov_is_pp_one_vf(adev))
@@ -7927,6 +7928,13 @@ static void gfx_v10_0_update_spm_vmid(struct 
amdgpu_device *adev, unsigned vmid)
                WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
        else
                WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
+}
+
+static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned 
vmid)
+{
+       amdgpu_gfx_off_ctrl(adev, false);
+
+       gfx_v10_0_update_spm_vmid_internal(adev, vmid);
 
        amdgpu_gfx_off_ctrl(adev, true);
 }
-- 
2.41.0