Acked-by: Alex Deucher <alexander.deuc...@amd.com>
On Wed, Jun 21, 2023 at 3:30 AM Evan Quan <evan.q...@amd.com> wrote: > > The feature mask bit was not correctly cleared. Without that, the L2H > and H2L interrupts cannot be enabled. > > Signed-off-by: Evan Quan <evan.q...@amd.com> > --- > drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c | 4 +++- > drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c | 4 +++- > 2 files changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c > b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c > index ed3dff0b52d2..ae342c58cd3e 100644 > --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c > +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c > @@ -192,7 +192,9 @@ static int vega12_thermal_set_temperature_range(struct > pp_hwmgr *hwmgr, > val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); > val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high); > val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low); > - val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); > + val &= ~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK; > + val &= ~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; > + val &= ~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; > > WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); > > diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c > b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c > index f4f4efdbda79..e9737ca8418a 100644 > --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c > +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c > @@ -263,7 +263,9 @@ static int vega20_thermal_set_temperature_range(struct > pp_hwmgr *hwmgr, > val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, > 1); > val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, > high); > val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, > low); > - val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); > + val &= ~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK; > + val &= ~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; > + val &= ~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; > > WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); > > -- > 2.34.1 >
