[AMD Official Use Only - General] Reviewed-by: Emily Deng <[email protected]>
>-----Original Message----- >From: amd-gfx <[email protected]> On Behalf Of Horace >Chen >Sent: Tuesday, June 20, 2023 9:30 PM >To: [email protected] >Cc: Andrey Grodzovsky <[email protected]>; Xiao, Jack ><[email protected]>; Xu, Feifei <[email protected]>; Chen, Horace ><[email protected]>; Chang, HaiJun <[email protected]>; >Deucher, Alexander <[email protected]>; Quan, Evan ><[email protected]>; Koenig, Christian <[email protected]>; Liu, >Monk <[email protected]>; Zhang, Hawking <[email protected]> >Subject: [PATCH] drm/amdgpu: Clear VCN cache when hw_init > >[Why] >VCN will use some framebuffer space as its cache. It needs to be reset when >reset happens, such as FLR. Otherwise some error may be kept after the reset. > >Signed-off-by: Horace Chen <[email protected]> >--- > drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 3 +++ > 1 file changed, 3 insertions(+) > >diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c >b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c >index b48bb5212488..2db73a964031 100644 >--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c >+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c >@@ -1292,6 +1292,7 @@ static int vcn_v4_0_start_sriov(struct >amdgpu_device *adev) > cache_size); > > cache_addr = adev->vcn.inst[i].gpu_addr + offset; >+ memset(adev->vcn.inst[i].cpu_addr + offset, 0, >+AMDGPU_VCN_STACK_SIZE); > > MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, > regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), > lower_32_bits(cache_addr)); >@@ -1307,6 +1308,8 @@ static int vcn_v4_0_start_sriov(struct >amdgpu_device *adev) > > cache_addr = adev->vcn.inst[i].gpu_addr + offset + > AMDGPU_VCN_STACK_SIZE; >+ memset(adev->vcn.inst[i].cpu_addr + offset + >AMDGPU_VCN_STACK_SIZE, 0, >+ AMDGPU_VCN_STACK_SIZE); > > MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, > regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), > lower_32_bits(cache_addr)); >-- >2.34.1
