[PATCH 1/3] drm/amd/pm: fix vclk setting failed for SMU v13.0.5

[Tim Huang]

PMFW use the left-shifted 16 bits argument to set the VCLK
DPM frequency for SMU v13.0.5.

Signed-off-by: Tim Huang <tim.hu...@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
index 7c3ac535f68a..725c791ad3fc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
@@ -831,6 +831,8 @@ static int smu_v13_0_5_set_soft_freq_limited_range(struct 
smu_context *smu,
                                                        uint32_t max)
 {
        enum smu_message_type msg_set_min, msg_set_max;
+       uint32_t min_clk = min;
+       uint32_t max_clk = max;
        int ret = 0;
 
        if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type))
@@ -851,11 +853,16 @@ static int smu_v13_0_5_set_soft_freq_limited_range(struct 
smu_context *smu,
                return -EINVAL;
        }
 
-       ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
+       if (clk_type == SMU_VCLK) {
+               min_clk = min << SMU_13_VCLK_SHIFT;
+               max_clk = max << SMU_13_VCLK_SHIFT;
+       }
+
+       ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL);
        if (ret)
                goto out;
 
-       ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max, NULL);
+       ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max_clk, NULL);
        if (ret)
                goto out;
 
-- 
2.34.1