Acked-by: Luben Tuikov <luben.tui...@amd.com>
Regards,
Luben
On 2023-04-06 06:13, Tong Liu01 wrote:
> [why]
> regGOLDEN_TSC_COUNT_LOWER/regGOLDEN_TSC_COUNT_UPPER are protected and
> unaccessible under sriov.
> The clock counter high bit may update during reading process.
>
> [How]
> Replace regGOLDEN_TSC_COUNT_LOWER/regGOLDEN_TSC_COUNT_UPPER with
> regCP_MES_MTIME_LO/regCP_MES_MTIME_HI to get gpu clock under sriov.
> Refine get gpu clock counter method to make the result more precise.
>
> Signed-off-by: Tong Liu01 <tong.li...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 17 +++++++++++++++--
> 1 file changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index ecf8ceb53311..107c487c0c37 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -4671,11 +4671,24 @@ static int gfx_v11_0_post_soft_reset(void *handle)
> static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev)
> {
> uint64_t clock;
> + uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after;
>
> amdgpu_gfx_off_ctrl(adev, false);
> mutex_lock(&adev->gfx.gpu_clock_mutex);
> - clock = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER) |
> - ((uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER) <<
> 32ULL);
> + if (amdgpu_sriov_vf(adev)) {
> + clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0,
> regCP_MES_MTIME_HI);
> + clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0,
> regCP_MES_MTIME_LO);
> + clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0,
> regCP_MES_MTIME_HI);
> + if (clock_counter_hi_pre != clock_counter_hi_after)
> + clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0,
> regCP_MES_MTIME_LO);
> + } else {
> + clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0,
> regGOLDEN_TSC_COUNT_UPPER);
> + clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0,
> regGOLDEN_TSC_COUNT_LOWER);
> + clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0,
> regGOLDEN_TSC_COUNT_UPPER);
> + if (clock_counter_hi_pre != clock_counter_hi_after)
> + clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0,
> regGOLDEN_TSC_COUNT_LOWER);
> + }
> + clock = clock_counter_lo | (clock_counter_hi_after << 32ULL);
> mutex_unlock(&adev->gfx.gpu_clock_mutex);
> amdgpu_gfx_off_ctrl(adev, true);
> return clock;
