Use dummy command submissions with a 0-sized IB on a compute VM to flush
TLBs and signal the fence in SW. This allows applications with user mode
queues to sync with asynchronous VM updates through the CS API.
Signed-off-by: Felix Kuehling <felix.kuehl...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index bcccc348dbe2..3f35d04bd4f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -171,6 +171,15 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
return -EINVAL;
}
+ if (ib->length_dw == 0 && vm->is_compute_context) {
+ /* Hack: Dummy CS. Just flush TLBs and signal the fence. */
+ r = amdgpu_amdkfd_flush_tlb(adev, vm, TLB_FLUSH_LEGACY);
+ if (r)
+ return r;
+ *f = &job->hw_fence;
+ return dma_fence_signal(*f);
+ }
+
alloc_size = ring->funcs->emit_frame_size + num_ibs *
ring->funcs->emit_ib_size;
--
2.34.1
