[PATCH AUTOSEL 6.1 38/58] drm/amd/display: fix FCLK pstate change underflow

[Sasha Levin]

From: Vladimir Stempen <vladimir.stem...@amd.com>

[ Upstream commit 972243f973eb0821084e5833d5f7f4ed025f42da ]

[Why]
Currently we set FCLK p-state change
watermark calculated based on dummy
p-state latency when UCLK p-state is
not supported

[How]
Calculate FCLK p-state change watermark
based on on FCLK pstate change latency
in case UCLK p-state is not supported

Reviewed-by: Nevenko Stupar <nevenko.stu...@amd.com>
Acked-by: Alex Hung <alex.h...@amd.com>
Signed-off-by: Vladimir Stempen <vladimir.stem...@amd.com>
Tested-by: Daniel Wheeler <daniel.whee...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Sasha Levin <sas...@kernel.org>
---
 drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index d90216d2fe3a8..04cc96e700981 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1963,6 +1963,10 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, 
struct dc_state *context,
                 */
                context->bw_ctx.bw.dcn.watermarks.a = 
context->bw_ctx.bw.dcn.watermarks.c;
                
context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;
+               /* Calculate FCLK p-state change watermark based on FCLK pstate 
change latency in case
+                * UCLK p-state is not supported, to avoid underflow in case 
FCLK pstate is supported
+                */
+               
context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = 
get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
        } else {
                /* Set A:
                 * All clocks min.
-- 
2.39.0