[PATCH 24/29] drm/amd/display: use uclk pstate latency for fw assisted mclk validation dcn32

[Tom Chung]

From: Dillon Varone <dillon.var...@amd.com>

[WHY?]
DCN32 uses fclk pstate watermarks for dummy pstate, and must always be
supported.

[HOW?]
Validation needs to be run with fclk pstate latency set
as the dummy pstate latency to get correct prefetch and bandwidth outputs.

Reviewed-by: Jun Lei <jun....@amd.com>
Acked-by: Tom Chung <chiahsuan.ch...@amd.com>
Signed-off-by: Dillon Varone <dillon.var...@amd.com>
---
 .../gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 51b4b1d0ba99..97b333b230d1 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1844,6 +1844,12 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, 
struct dc_state *context,
                         */
                        context->bw_ctx.dml.soc.dram_clock_change_latency_us =
                                        
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
+                       /* For DCN32/321 need to validate with fclk pstate 
change latency equal to dummy so
+                        * prefetch is scheduled correctly to account for dummy 
pstate.
+                        */
+                       if (dummy_latency_index == 0)
+                               context->bw_ctx.dml.soc.fclk_change_latency_us =
+                                               
dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
                        dcn32_internal_validate_bw(dc, context, pipes, 
&pipe_cnt, &vlevel, false);
                        maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
                        dcfclk_from_fw_based_mclk_switching = 
context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
@@ -2031,6 +2037,10 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, 
struct dc_state *context,
 
        context->perf_params.stutter_period_us = 
context->bw_ctx.dml.vba.StutterPeriod;
 
+       if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && 
dummy_latency_index == 0)
+               context->bw_ctx.dml.soc.fclk_change_latency_us =
+                               
dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
+
        dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
 
        if (!pstate_en)
@@ -2038,8 +2048,12 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, 
struct dc_state *context,
                context->bw_ctx.dml.soc.dram_clock_change_latency_us =
                                
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
 
-       if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)
+       if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
                dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(dc, 
context);
+               if (dummy_latency_index == 0)
+                       context->bw_ctx.dml.soc.fclk_change_latency_us =
+                                       
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;
+       }
 }
 
 static void dcn32_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
-- 
2.25.1