[AMD Official Use Only - General]
Reviewed-by: Kent Russell <kent.russ...@amd.com>
> -----Original Message-----
> From: amd-gfx <amd-gfx-boun...@lists.freedesktop.org> On Behalf Of Luben
> Tuikov
> Sent: Monday, November 7, 2022 12:44 PM
> To: AMD Graphics <amd-gfx@lists.freedesktop.org>
> Cc: Zhou1, Tao <tao.zh...@amd.com>; Deucher, Alexander
> <alexander.deuc...@amd.com>; Tuikov, Luben <luben.tui...@amd.com>; Li,
> Candice <candice...@amd.com>
> Subject: [PATCH] drm/amdgpu: Decouple RAS EEPROM addresses from chips
>
> Abstract RAS I2C EEPROM addresses from chip names, and set their macro
> definition names to the address they set, not the chip they attach
> to. Since most chips either use I2C EEPROM address 0 or 40000h for the RAS
> table start offset, this leaves with only two macro definitions as opposed
> to five, and removes the redundancy of four.
>
> Cc: Candice Li <candice...@amd.com>
> Cc: Tao Zhou <tao.zh...@amd.com>
> Cc: Alex Deucher <alexander.deuc...@amd.com>
> Signed-off-by: Luben Tuikov <luben.tui...@amd.com>
> ---
> .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 23 +++++++++----------
> 1 file changed, 11 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> index 1bb92a64f24afc..f63bd31e199c8e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> @@ -51,12 +51,11 @@
> * Depending on the size of the I2C EEPROM device(s), bits 18:16 may
> * address memory in a device or a device on the I2C bus, depending on
> * the status of pins 1-3. See top of amdgpu_eeprom.c.
> + *
> + * The RAS table lives either at address 0 or address 40000h of EEPROM.
> */
> -#define EEPROM_I2C_MADDR_VEGA20 0x0
> -#define EEPROM_I2C_MADDR_ARCTURUS 0x40000
> -#define EEPROM_I2C_MADDR_ARCTURUS_D342 0x0
> -#define EEPROM_I2C_MADDR_SIENNA_CICHLID 0x0
> -#define EEPROM_I2C_MADDR_ALDEBARAN 0x0
> +#define EEPROM_I2C_MADDR_0 0x0
> +#define EEPROM_I2C_MADDR_4 0x40000
>
> /*
> * The 2 macros bellow represent the actual size in bytes that
> @@ -135,9 +134,9 @@ static bool __get_eeprom_i2c_addr_arct(struct
> amdgpu_device *adev,
> if (strnstr(atom_ctx->vbios_version,
> "D342",
> sizeof(atom_ctx->vbios_version)))
> - control->i2c_address =
> EEPROM_I2C_MADDR_ARCTURUS_D342;
> + control->i2c_address = EEPROM_I2C_MADDR_0;
> else
> - control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS;
> + control->i2c_address = EEPROM_I2C_MADDR_4;
>
> return true;
> }
> @@ -148,7 +147,7 @@ static bool __get_eeprom_i2c_addr_ip_discovery(struct
> amdgpu_device *adev,
> switch (adev->ip_versions[MP1_HWIP][0]) {
> case IP_VERSION(13, 0, 0):
> case IP_VERSION(13, 0, 10):
> - control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS;
> + control->i2c_address = EEPROM_I2C_MADDR_4;
> return true;
> default:
> return false;
> @@ -180,18 +179,18 @@ static bool __get_eeprom_i2c_addr(struct
> amdgpu_device *adev,
>
> switch (adev->asic_type) {
> case CHIP_VEGA20:
> - control->i2c_address = EEPROM_I2C_MADDR_VEGA20;
> + control->i2c_address = EEPROM_I2C_MADDR_0;
> break;
>
> case CHIP_ARCTURUS:
> return __get_eeprom_i2c_addr_arct(adev, control);
>
> case CHIP_SIENNA_CICHLID:
> - control->i2c_address =
> EEPROM_I2C_MADDR_SIENNA_CICHLID;
> + control->i2c_address = EEPROM_I2C_MADDR_0;
> break;
>
> case CHIP_ALDEBARAN:
> - control->i2c_address = EEPROM_I2C_MADDR_ALDEBARAN;
> + control->i2c_address = EEPROM_I2C_MADDR_0;
> break;
>
> case CHIP_IP_DISCOVERY:
> @@ -203,7 +202,7 @@ static bool __get_eeprom_i2c_addr(struct
> amdgpu_device *adev,
>
> switch (adev->ip_versions[MP1_HWIP][0]) {
> case IP_VERSION(13, 0, 0):
> - control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS;
> + control->i2c_address = EEPROM_I2C_MADDR_4;
> break;
>
> default:
>
> base-commit: 03b61a92efbaf17ac3d9f82ae81aa4cf8ed40608
> prerequisite-patch-id: 6ba70460570b30bf3176058b399934e5e79b229e
> --
> 2.38.1
