[PATCH 15/33] drm/amd/display: Limit dcn32 to 1950Mhz display clock

[Rodrigo Siqueira]

From: Jun Lei <jun....@amd.com>

[why]
Hardware team recommends we limit dispclock to 1950Mhz for all DCN3.2.x

[how]
Limit to 1950 when initializing clocks.

Reviewed-by: Alvin Lee <alvin.l...@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.sique...@amd.com>
Signed-off-by: Jun Lei <jun....@amd.com>
---
 .../gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c  | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 1c612ccf1944..fd0313468fdb 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -157,6 +157,7 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
        struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
        unsigned int num_levels;
        struct clk_limit_num_entries *num_entries_per_clk = 
&clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
+       unsigned int i;
 
        memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
        clk_mgr_base->clks.p_state_change_support = true;
@@ -205,18 +206,17 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
                clk_mgr->dpm_present = true;
 
        if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {
-               unsigned int i;
-
                for (i = 0; i < num_levels; i++)
                        if 
(clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
                                        < 
khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))
                                
clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
                                        = 
khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);
        }
+       for (i = 0; i < num_levels; i++)
+               if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz > 
1950)
+                       
clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz = 1950;
 
        if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {
-               unsigned int i;
-
                for (i = 0; i < num_levels; i++)
                        if 
(clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
                                        < 
khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))
-- 
2.35.1