[Public]
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
________________________________
From: amd-gfx <amd-gfx-boun...@lists.freedesktop.org> on behalf of Tom St Denis
<tom.stde...@amd.com>
Sent: Friday, September 23, 2022 8:56 AM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Cc: StDenis, Tom <tom.stde...@amd.com>
Subject: [PATCH] drm/amd/amdgpu: Add missing XGMI hive registers for mmhub 9.4.1
These are used by umr to sort the hive nodes since the kernel
initializes the nodes in order of bus enumeration not XGMI hive
enumeration.
Signed-off-by: Tom St Denis <tom.stde...@amd.com>
---
.../drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h | 4 ++++
.../drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h | 8 ++++++++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h
index d8632ccf3494..c488d4a50cf4 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h
@@ -4409,6 +4409,10 @@
#define mmVMSHAREDPF0_MC_VM_XGMI_LFB_SIZE_BASE_IDX
1
#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL
0x0af9
#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX
1
+#define mmMC_VM_XGMI_LFB_CNTL
0x0823
+#define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX
0
+#define mmMC_VM_XGMI_LFB_SIZE
0x0824
+#define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX
0
// addressBlock: mmhub_utcl2_vmsharedvcdec
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h
b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h
index 111a71b434e2..2969fbf282b7 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h
@@ -26728,6 +26728,14 @@
//VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL
#define
VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT
0x0
#define
VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK
0x00000001L
+//MC_VM_XGMI_LFB_CNTL
+#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT
0x0
+#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT
0x3
+#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK
0x00000007L
+#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK
0x00000038L
+//MC_VM_XGMI_LFB_SIZE
+#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT
0x0
+#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK
0x0000FFFFL
// addressBlock: mmhub_utcl2_vmsharedvcdec
--
2.34.1
