Re: [PATCH] drm/amdgpu: add sdma instance check for gfx11 CGCG

[Zhang, Yifan]

[AMD Official Use Only - General]

This series is:

Reviewed-by: Yifan Zhang

________________________________
发件人: Huang, Tim <tim.hu...@amd.com>
发送时间: Monday, August 22, 2022 2:36:41 PM
收件人: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
抄送: Deucher, Alexander <alexander.deuc...@amd.com>; Zhang, Yifan 
<yifan1.zh...@amd.com>; Du, Xiaojian <xiaojian...@amd.com>; Zhang, Hawking 
<hawking.zh...@amd.com>; wenhui.sh...@amd.com <wenhui.sh...@amd.com>; Huang, 
Tim <tim.hu...@amd.com>
主题: [PATCH] drm/amdgpu: add sdma instance check for gfx11 CGCG

For some ASICs, like GFX IP v11.0.1, only have one SDMA instance,
so not need to configure SDMA1_RLC_CGCG_CTRL for this case.

Signed-off-by: Tim Huang <tim.hu...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index f45db80810fa..e8db772e068c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -5182,9 +5182,12 @@ static void 
gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
                 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, 
CGCG_INT_ENABLE, 1);
                 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);

-               data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
-               data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, 
CGCG_INT_ENABLE, 1);
-               WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
+               /* Some ASICs only have one SDMA instance, not need to 
configure SDMA1 */
+               if (adev->sdma.num_instances > 1) {
+                       data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
+                       data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, 
CGCG_INT_ENABLE, 1);
+                       WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
+               }
         } else {
                 /* Program RLC_CGCG_CGLS_CTRL */
                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
@@ -5213,9 +5216,12 @@ static void 
gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
                 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
                 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);

-               data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
-               data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
-               WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
+               /* Some ASICs only have one SDMA instance, not need to 
configure SDMA1 */
+               if (adev->sdma.num_instances > 1) {
+                       data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
+                       data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
+                       WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
+               }
         }
 }

--
2.25.1