[AMD Official Use Only]
Hi Stanley,
The flag is set by RAS block poison irq handler, such as vcn/jpeg poison irq
handler. It's not configured in RAS init.
Regards,
Tao
> -----Original Message-----
> From: Yang, Stanley <stanley.y...@amd.com>
> Sent: Monday, April 11, 2022 10:12 PM
> To: Zhou1, Tao <tao.zh...@amd.com>; amd-gfx@lists.freedesktop.org; Lazar,
> Lijo <lijo.la...@amd.com>; Ziya, Mohammad zafar
> <mohammadzafar.z...@amd.com>; Zhang, Hawking
> <hawking.zh...@amd.com>; Chai, Thomas <yipeng.c...@amd.com>
> Subject: 回复: [PATCH 1/3] drm/amdgpu: add poison consumption flag for RAS
> IH
>
> [AMD Official Use Only]
>
> Hi Tao,
>
> According to the series patches, I have one question, is the ras_ih_flag set
> according to poison mode configuration, if yes, driver will handle poison once
> get ecc_irq interrupt, but at this moment there may no app to consumes it,
> this
> seems conflict the poison consumption definition.
>
> Regards,
> Stanley
> > -----邮件原件-----
> > 发件人: Zhou1, Tao <tao.zh...@amd.com>
> > 发送时间: Monday, April 11, 2022 7:08 PM
> > 收件人: amd-gfx@lists.freedesktop.org; Lazar, Lijo <lijo.la...@amd.com>;
> > Ziya, Mohammad zafar <mohammadzafar.z...@amd.com>; Zhang, Hawking
> > <hawking.zh...@amd.com>; Yang, Stanley <stanley.y...@amd.com>; Chai,
> > Thomas <yipeng.c...@amd.com>
> > 抄送: Zhou1, Tao <tao.zh...@amd.com>
> > 主题: [PATCH 1/3] drm/amdgpu: add poison consumption flag for RAS IH
> >
> > So we can distinguish RAS poison consumption interrupt from UE interrupt.
> >
> > Signed-off-by: Tao Zhou <tao.zh...@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
> > index 606df8869b89..380f4c3020c7 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
> > @@ -314,6 +314,11 @@ enum amdgpu_ras_ret {
> > AMDGPU_RAS_PT,
> > };
> >
> > +enum amdgpu_ras_ih_flag {
> > + AMDGPU_RAS_IH_POISON_CONSUMPTION = 0,
> > + AMDGPU_RAS_IH_LAST,
> > +};
> > +
> > struct ras_common_if {
> > enum amdgpu_ras_block block;
> > enum amdgpu_ras_error_type type; @@ -419,6 +424,8 @@ struct
> > ras_ih_data {
> > unsigned int aligned_element_size;
> > unsigned int rptr;
> > unsigned int wptr;
> > + /* interrupt type flag */
> > + unsigned int flag;
> > };
> >
> > struct ras_manager {
> > --
> > 2.35.1
>
