Thanks for your suggestion, it’s better to centralize umc mca status check in a
helper function, will update.
Regards,
Stanley
> -----邮件原件-----
> 发件人: Zhang, Hawking <hawking.zh...@amd.com>
> 发送时间: Friday, April 8, 2022 11:11 AM
> 收件人: Zhou1, Tao <tao.zh...@amd.com>; Yang, Stanley
> <stanley.y...@amd.com>; amd-gfx@lists.freedesktop.org; Li, Candice
> <candice...@amd.com>
> 抄送: Yang, Stanley <stanley.y...@amd.com>
> 主题: RE: [PATCH Review 1/1] drm/amdgpu: print more correctable error
> info
>
> We shall consider centralize UMC MCA status check in a helper function, at
> least, querying IPID, SYND, and MCA_STATUS should be the same for both ue
> and ce.
>
> Regards,
> Hawking
>
> -----Original Message-----
> From: Zhou1, Tao <tao.zh...@amd.com>
> Sent: Friday, April 8, 2022 10:59
> To: Yang, Stanley <stanley.y...@amd.com>; amd-gfx@lists.freedesktop.org;
> Zhang, Hawking <hawking.zh...@amd.com>; Li, Candice
> <candice...@amd.com>
> Cc: Yang, Stanley <stanley.y...@amd.com>
> Subject: RE: [PATCH Review 1/1] drm/amdgpu: print more correctable error
> info
>
> [AMD Official Use Only]
>
>
>
> > -----Original Message-----
> > From: Stanley.Yang <stanley.y...@amd.com>
> > Sent: Friday, April 8, 2022 10:18 AM
> > To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
> > <hawking.zh...@amd.com>; Zhou1, Tao <tao.zh...@amd.com>; Li,
> Candice
> > <candice...@amd.com>
> > Cc: Yang, Stanley <stanley.y...@amd.com>
> > Subject: [PATCH Review 1/1] drm/amdgpu: print more correctable error
> > info
> >
>
> [Tao] it's better to add description for the patch.
>
> > Change-Id: I09a2aae85cde3ab2cb6b042b973da6839ad024ec
> > Signed-off-by: Stanley.Yang <stanley.y...@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/umc_v6_7.c | 62
> > ++++++++++++++++++++++++++-
> > 1 file changed, 60 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
> > b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
> > index c45d9c14ecbc..803119f75e39 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
> > @@ -70,15 +70,46 @@ static void
> > umc_v6_7_ecc_info_query_correctable_error_count(struct amdgpu_device
> {
> > uint64_t mc_umc_status;
> > uint32_t eccinfo_table_idx;
> > + uint32_t umc_reg_offset;
> > + uint32_t mc_umc_addr;
> > + uint64_t reg_value;
> > struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
> >
> > + umc_reg_offset = get_umc_v6_7_reg_offset(adev,
> > + umc_inst, ch_inst);
> > +
> > eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num +
> ch_inst;
> > /* check for SRAM correctable error
> > MCUMC_STATUS is a 64 bit register */
> > mc_umc_status = ras-
> > >umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
> > if (REG_GET_FIELD(mc_umc_status,
> > MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
> > - REG_GET_FIELD(mc_umc_status,
> > MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
> > + REG_GET_FIELD(mc_umc_status,
> > MCA_UMC_UMC0_MCUMC_STATUST0, CECC) ==
> > +1) {
> > *error_count += 1;
> > +
> > + if (mc_umc_status)
> > + dev_info(adev->dev, "MCA STATUS 0x%llx,
> > umc_reg_offset 0x%x\n",
> > +mc_umc_status, umc_reg_offset);
> > +
> > + /* print IPID registers value */
> > + mc_umc_addr =
> > + SOC15_REG_OFFSET(UMC, 0,
> > regMCA_UMC_UMC0_MCUMC_IPIDT0);
> > + reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset)
> *
> > 4);
> > + if (reg_value)
> > + dev_info(adev->dev, "MCA IPID 0x%llx,
> umc_reg_offset
> > 0x%x\n",
> > +reg_value, umc_reg_offset);
> > +
> > + /* print SYND registers value */
> > + mc_umc_addr =
> > + SOC15_REG_OFFSET(UMC, 0,
> > regMCA_UMC_UMC0_MCUMC_SYNDT0);
> > + reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset)
> *
> > 4);
> > + if (reg_value)
> > + dev_info(adev->dev, "MCA SYND 0x%llx,
> > umc_reg_offset 0x%x\n",
> > +reg_value, umc_reg_offset);
> > +
> > + /* print MISC0 registers value */
> > + mc_umc_addr =
> > + SOC15_REG_OFFSET(UMC, 0,
> > regMCA_UMC_UMC0_MCUMC_MISC0T0);
> > + reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset)
> *
> > 4);
> > + if (reg_value)
> > + dev_info(adev->dev, "MCA MISC0 0x%llx,
> > umc_reg_offset 0x%x\n", reg_value, umc_reg_offset);
> > + }
>
> [Tao] can we implement a query_error_status function and:
>
> 1. call query_error_status in xxx_error_count function, like this patch, or 2.
> register it to adev->umc.ras and call it in amdgpu_ras_get_ecc_info.
>
> > }
> >
> > static void umc_v6_7_ecc_info_querry_uncorrectable_error_count(struct
> > amdgpu_device *adev, @@ -242,7 +273,9 @@ static void
> > umc_v6_7_query_correctable_error_count(struct amdgpu_device *adev,
> > uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
> > uint32_t ecc_err_cnt, ecc_err_cnt_addr;
> > uint64_t mc_umc_status;
> > + uint32_t mc_umc_addr;
> > uint32_t mc_umc_status_addr;
> > + uint64_t reg_value;
> >
> > /* UMC 6_1_1 registers */
> > ecc_err_cnt_sel_addr =
> > @@ -277,8 +310,33 @@ static void
> > umc_v6_7_query_correctable_error_count(struct amdgpu_device *adev,
> > MCUMC_STATUS is a 64 bit register */
> > mc_umc_status = RREG64_PCIE((mc_umc_status_addr +
> > umc_reg_offset) * 4);
> > if (REG_GET_FIELD(mc_umc_status,
> > MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
> > - REG_GET_FIELD(mc_umc_status,
> > MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
> > + REG_GET_FIELD(mc_umc_status,
> > MCA_UMC_UMC0_MCUMC_STATUST0, CECC) ==
> > +1) {
> > *error_count += 1;
> > +
> > + if (mc_umc_status)
> > + dev_info(adev->dev, "MCA STATUS 0x%llx,
> > umc_reg_offset 0x%x\n",
> > +mc_umc_status, umc_reg_offset);
> > +
> > + /* print IPID registers value */
> > + mc_umc_addr =
> > + SOC15_REG_OFFSET(UMC, 0,
> > regMCA_UMC_UMC0_MCUMC_IPIDT0);
> > + reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset)
> *
> > 4);
> > + if (reg_value)
> > + dev_info(adev->dev, "MCA IPID 0x%llx,
> umc_reg_offset
> > 0x%x\n",
> > +reg_value, umc_reg_offset);
> > +
> > + /* print SYND registers value */
> > + mc_umc_addr =
> > + SOC15_REG_OFFSET(UMC, 0,
> > regMCA_UMC_UMC0_MCUMC_SYNDT0);
> > + reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset)
> *
> > 4);
> > + if (reg_value)
> > + dev_info(adev->dev, "MCA SYND 0x%llx,
> > umc_reg_offset 0x%x\n",
> > +reg_value, umc_reg_offset);
> > +
> > + /* print MISC0 registers value */
> > + mc_umc_addr =
> > + SOC15_REG_OFFSET(UMC, 0,
> > regMCA_UMC_UMC0_MCUMC_MISC0T0);
> > + reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset)
> *
> > 4);
> > + if (reg_value)
> > + dev_info(adev->dev, "MCA MISC0 0x%llx,
> > umc_reg_offset 0x%x\n", reg_value, umc_reg_offset);
> > + }
> > }
> >
> > static void umc_v6_7_querry_uncorrectable_error_count(struct
> > amdgpu_device *adev,
> > --
> > 2.17.1
