[PATCH 13/21] drm/amd/display: enable dcn315/316 s0i2 support

[Alan Liu]

From: Charlene Liu <charlene....@amd.com>

[why]
enable the support in driver, let the control by CMOS

Reviewed-by: Aric Cyr <aric....@amd.com>
Acked-by: Alan Liu <haoping....@amd.com>
Signed-off-by: Charlene Liu <charlene....@amd.com>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 2 +-
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c | 3 +--
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
index 48fab0a0c08b..edda572dc570 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
@@ -131,6 +131,7 @@ static void dcn315_update_clocks(struct clk_mgr 
*clk_mgr_base,
                                union display_idle_optimization_u idle_info = { 
0 };
                                idle_info.idle_info.df_request_disabled = 1;
                                idle_info.idle_info.phy_ref_clk_off = 1;
+                               idle_info.idle_info.s0i2_rdy = 1;
                                
dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
                                /* update power state */
                                clk_mgr_base->clks.pwr_state = 
DCN_PWR_STATE_LOW_POWER;
@@ -526,7 +527,6 @@ void dcn315_clk_mgr_construct(
                struct dccg *dccg)
 {
        struct dcn315_smu_dpm_clks smu_dpm_clks = { 0 };
-       struct clk_mgr *clk_mgr_base = ctx->dc->clk_mgr;
 
        clk_mgr->base.base.ctx = ctx;
        clk_mgr->base.base.funcs = &dcn315_funcs;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
index c940635b7a74..43120a8f8305 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
@@ -172,8 +172,7 @@ static void dcn316_update_clocks(struct clk_mgr 
*clk_mgr_base,
                                union display_idle_optimization_u idle_info = { 
0 };
                                idle_info.idle_info.df_request_disabled = 1;
                                idle_info.idle_info.phy_ref_clk_off = 1;
-                               // Todo DCN316 set this to 1 if any no issue
-                               idle_info.idle_info.s0i2_rdy = 0;
+                               idle_info.idle_info.s0i2_rdy = 1;
                                
dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
                                /* update power state */
                                clk_mgr_base->clks.pwr_state = 
DCN_PWR_STATE_LOW_POWER;
-- 
2.25.1