[AMD Official Use Only]
> -----Original Message-----
> From: Lazar, Lijo <lijo.la...@amd.com>
> Sent: Monday, December 13, 2021 2:52 PM
> To: Quan, Evan <evan.q...@amd.com>; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <alexander.deuc...@amd.com>
> Subject: Re: [PATCH] drm/amdgpu: move smu_debug_mask to a more
> proper place
>
>
>
> On 12/13/2021 11:12 AM, Evan Quan wrote:
> > As the smu_context will be invisible from outside(of power). Also, the
> > smu_debug_mask can be shared around all power code instead of some
> > specific framework(swSMU) only.
> >
> > Signed-off-by: Evan Quan <evan.q...@amd.com>
> > Change-Id: I1a0e1a436a51fc520a47b3fb28cde527d4e5eb6e
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 +++++++
> > drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 +-
> > drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 8 --------
> > drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 9 ++++++---
> > 4 files changed, 14 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index e701dedce344..9ceb8f3e73de 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -811,6 +811,9 @@ struct amd_powerplay {
> > (rid == 0x01) || \
> > (rid == 0x10))))
> >
> > +/* Used to mask smu debug modes */
> > +#define SMU_DEBUG_HALT_ON_ERROR 0x1
> > +
> > #define AMDGPU_RESET_MAGIC_NUM 64
> > #define AMDGPU_MAX_DF_PERFMONS 4
> > struct amdgpu_device {
> > @@ -959,6 +962,10 @@ struct amdgpu_device {
> > struct amdgpu_pm pm;
> > u32 cg_flags;
> > u32 pg_flags;
> > + /*
> > + * 0 = disabled (default), otherwise enable corresponding debug
> mode
> > + */
> > + uint32_t smu_debug_mask;
> >
> Maybe, better to have it inside pm.
[Quan, Evan] Thanks. Fixed in V2.
BR
Evan
>
> Thanks,
> Lijo
>
> > /* nbio */
> > struct amdgpu_nbio nbio;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> > index 9dfccb20fedd..ee1cc15c6f09 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> > @@ -1619,7 +1619,7 @@ int amdgpu_debugfs_init(struct amdgpu_device
> *adev)
> > return 0;
> >
> > debugfs_create_x32("amdgpu_smu_debug", 0600, root,
> > - &adev->smu.smu_debug_mask);
> > + &adev->smu_debug_mask);
> >
> > ent = debugfs_create_file("amdgpu_preempt_ib", 0600, root, adev,
> > &fops_ib_preempt);
> > diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> > b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> > index 12e67ad9a3b2..2b9b9a7ba97a 100644
> > --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> > +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> > @@ -482,9 +482,6 @@ struct stb_context {
> >
> > #define WORKLOAD_POLICY_MAX 7
> >
> > -/* Used to mask smu debug modes */
> > -#define SMU_DEBUG_HALT_ON_ERROR 0x1
> > -
> > struct smu_context
> > {
> > struct amdgpu_device *adev;
> > @@ -573,11 +570,6 @@ struct smu_context
> > struct smu_user_dpm_profile user_dpm_profile;
> >
> > struct stb_context stb_context;
> > -
> > - /*
> > - * 0 = disabled (default), otherwise enable corresponding debug
> mode
> > - */
> > - uint32_t smu_debug_mask;
> > };
> >
> > struct i2c_adapter;
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> > index 43637d55fe29..b233d9d766f2 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> > @@ -257,6 +257,7 @@ int smu_cmn_send_msg_without_waiting(struct
> smu_context *smu,
> > uint16_t msg_index,
> > uint32_t param)
> > {
> > + struct amdgpu_device *adev = smu->adev;
> > u32 reg;
> > int res;
> >
> > @@ -272,7 +273,7 @@ int smu_cmn_send_msg_without_waiting(struct
> smu_context *smu,
> > __smu_cmn_send_msg(smu, msg_index, param);
> > res = 0;
> > Out:
> > - if (unlikely(smu->smu_debug_mask &
> SMU_DEBUG_HALT_ON_ERROR) &&
> > + if (unlikely(adev->smu_debug_mask &
> SMU_DEBUG_HALT_ON_ERROR) &&
> > res && (res != -ETIME)) {
> > amdgpu_device_halt(smu->adev);
> > WARN_ON(1);
> > @@ -293,13 +294,14 @@ int smu_cmn_send_msg_without_waiting(struct
> smu_context *smu,
> > */
> > int smu_cmn_wait_for_response(struct smu_context *smu)
> > {
> > + struct amdgpu_device *adev = smu->adev;
> > u32 reg;
> > int res;
> >
> > reg = __smu_cmn_poll_stat(smu);
> > res = __smu_cmn_reg2errno(smu, reg);
> >
> > - if (unlikely(smu->smu_debug_mask &
> SMU_DEBUG_HALT_ON_ERROR) &&
> > + if (unlikely(adev->smu_debug_mask &
> SMU_DEBUG_HALT_ON_ERROR) &&
> > res && (res != -ETIME)) {
> > amdgpu_device_halt(smu->adev);
> > WARN_ON(1);
> > @@ -343,6 +345,7 @@ int smu_cmn_send_smc_msg_with_param(struct
> smu_context *smu,
> > uint32_t param,
> > uint32_t *read_arg)
> > {
> > + struct amdgpu_device *adev = smu->adev;
> > int res, index;
> > u32 reg;
> >
> > @@ -372,7 +375,7 @@ int smu_cmn_send_smc_msg_with_param(struct
> smu_context *smu,
> > if (read_arg)
> > smu_cmn_read_arg(smu, read_arg);
> > Out:
> > - if (unlikely(smu->smu_debug_mask &
> SMU_DEBUG_HALT_ON_ERROR) && res) {
> > + if (unlikely(adev->smu_debug_mask &
> SMU_DEBUG_HALT_ON_ERROR) && res)
> > +{
> > amdgpu_device_halt(smu->adev);
> > WARN_ON(1);
> > }
> >
