[PATCH 11/33] drm/amd/display: restyle dcn31 resource header inline with other asics

[Rodrigo Siqueira]

From: Dmytro Laktyushkin <dmytro.laktyush...@amd.com>

Style change for better consistency across codebase

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlaus...@amd.com>
Acked-by: Agustin Gutierrez <agustin.gutier...@amd.com>
Signed-off-by: Dmytro Laktyushkin <dmytro.laktyush...@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c |  4 ++--
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h | 10 ++++++++++
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index abbfb5aeff2a..2de731e3e639 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1828,7 +1828,7 @@ static int dcn31_populate_dml_pipes_from_context(
        return pipe_cnt;
 }
 
-static void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
+void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
 {
        if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
                context->bw_ctx.dml.soc.dram_clock_change_latency_us = 
dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
@@ -1972,7 +1972,7 @@ static void dcn31_calculate_wm_and_dlg_fp(
        dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
 }
 
-static void dcn31_calculate_wm_and_dlg(
+void dcn31_calculate_wm_and_dlg(
                struct dc *dc, struct dc_state *context,
                display_e2e_pipe_params_st *pipes,
                int pipe_cnt,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
index 93571c976996..416fe7a721d8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
@@ -35,6 +35,16 @@ struct dcn31_resource_pool {
        struct resource_pool base;
 };
 
+bool dcn31_validate_bandwidth(struct dc *dc,
+               struct dc_state *context,
+               bool fast_validate);
+void dcn31_calculate_wm_and_dlg(
+               struct dc *dc, struct dc_state *context,
+               display_e2e_pipe_params_st *pipes,
+               int pipe_cnt,
+               int vlevel);
+void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
+
 struct resource_pool *dcn31_create_resource_pool(
                const struct dc_init_data *init_data,
                struct dc *dc);
-- 
2.25.1