Two DP2 headers are available in drm that local ones should be removed.
Will submit a separate drm patch for all other DP2 required headers.
Signed-off-by: Fangzhi Zuo <jerry....@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 10 +++++-----
drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c | 4 ++++
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 7 -------
3 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 120c9955cafb..6be944ac46e2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -146,7 +146,7 @@ static uint32_t get_eq_training_aux_rd_interval(
if (dp_get_link_encoding_format(link_settings) ==
DP_128b_132b_ENCODING) {
core_link_read_dpcd(
link,
- DP_128b_132b_TRAINING_AUX_RD_INTERVAL,
+ DP_128B132B_TRAINING_AUX_RD_INTERVAL,
(uint8_t *)&training_rd_interval,
sizeof(training_rd_interval));
} else if (dp_get_link_encoding_format(link_settings) ==
DP_8b_10b_ENCODING &&
@@ -2107,7 +2107,7 @@ static void dpcd_128b_132b_get_aux_rd_interval(struct
dc_link *link,
uint32_t interval_unit = 0;
dpcd_interval.raw = 0;
- core_link_read_dpcd(link, DP_128b_132b_TRAINING_AUX_RD_INTERVAL,
+ core_link_read_dpcd(link, DP_128B132B_TRAINING_AUX_RD_INTERVAL,
&dpcd_interval.raw, sizeof(dpcd_interval.raw));
interval_unit = dpcd_interval.bits.UNIT ? 1 : 2; /* 0b = 2 ms, 1b = 1
ms */
/* (128b/132b_TRAINING_AUX_RD_INTERVAL value + 1) *
@@ -4593,7 +4593,7 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw =
- lttpr_dpcd_data[DP_PHY_REPEATER_128b_132b_RATES
-
+ lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES -
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
#endif
@@ -4875,13 +4875,13 @@ static bool retrieve_link_cap(struct dc_link *link)
link->dpcd_sink_ext_caps.raw = 0;
#if defined(CONFIG_DRM_AMD_DC_DCN)
- link->dpcd_caps.channel_coding_cap.raw =
dpcd_data[DP_MAIN_LINK_CHANNEL_CODING_CAP - DP_DPCD_REV];
+ link->dpcd_caps.channel_coding_cap.raw =
dpcd_data[DP_MAIN_LINK_CHANNEL_CODING - DP_DPCD_REV];
if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {
DC_LOG_DP2("128b/132b encoding is supported at link %d",
link->link_index);
core_link_read_dpcd(link,
- DP_128b_132b_SUPPORTED_LINK_RATES,
+ DP_128B132B_SUPPORTED_LINK_RATES,
&link->dpcd_caps.dp_128b_132b_supported_link_rates.raw,
sizeof(link->dpcd_caps.dp_128b_132b_supported_link_rates.raw));
if
(link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR20)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c
index 7f25c11f4248..ff06d6060e9a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c
@@ -127,7 +127,11 @@ static uint32_t dpcd_get_next_partition_size(const
uint32_t address, const uint3
* XXX: Do not allow any two address ranges in this array to overlap
*/
static const struct dpcd_address_range mandatory_dpcd_blocks[] = {
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+ { DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
DP_PHY_REPEATER_128B132B_RATES }};
+#else
{ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT }};
+#endif
/*
* extend addresses to read all mandatory blocks together
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index a5e798b5da79..04a71e10bb97 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -860,14 +860,10 @@ struct psr_caps {
};
#if defined(CONFIG_DRM_AMD_DC_DCN)
-#define DP_MAIN_LINK_CHANNEL_CODING_CAP 0x006
-#define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020
#define DP_FEC_CAPABILITY_1 0x091
#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
#define DP_DSC_CONFIGURATION 0x161
#define DP_PHY_SQUARE_PATTERN 0x249
-#define DP_128b_132b_SUPPORTED_LINK_RATES 0x2215
-#define DP_128b_132b_TRAINING_AUX_RD_INTERVAL 0x2216
#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0X2230
#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250
#define DP_DSC_SUPPORT_AND_DECODER_COUNT 0x2260
@@ -877,9 +873,6 @@ struct psr_caps {
# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
# define DP_DSC_DECODER_COUNT_SHIFT 5
-#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
-#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
-#define DP_PHY_REPEATER_128b_132b_RATES 0xF0007
#define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022
#define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3)
/* TODO - Use DRM header to replace above once available */
--
2.25.1
