[AMD Official Use Only]
That is not how the register works. The *16 has nothing to do with cu counts.
This is to address the upper and lower 16 bits in the register as each half of
the register programs a separate SH.
________________________________
From: Huang, Ray <ray.hu...@amd.com>
Sent: Thursday, September 23, 2021, 12:42 AM
To: amd-gfx@lists.freedesktop.org
Cc: Kuehling, Felix; Keely, Sean; Deucher, Alexander; Yu, Lang; Gong, Curry;
Huang, Ray
Subject: [PATCH 1/2] drm/amdgpu: fix to use real compute unit number for shader
array mask
We should use the real compute unit number for shader array mask. Some
asic doesn't have 16 compute units per shader array.
Signed-off-by: Huang Rui <ray.hu...@amd.com>
---
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
index c021519af810..0891c937f4da 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
@@ -159,12 +159,12 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
se_mask[i] = 0;
i = 0;
- for (cu = 0; cu < 16; cu++) {
+ for (cu = 0; cu < cu_info.num_cu_per_sh; cu++) {
for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++) {
for (se = 0; se < cu_info.num_shader_engines; se++) {
if (cu_per_sh[se][sh] > cu) {
if (cu_mask[i / 32] & (1 << (i % 32)))
- se_mask[se] |= 1 << (cu + sh *
16);
+ se_mask[se] |= 1 << (cu + sh *
cu_info.num_cu_per_sh);
i++;
if (i == cu_mask_count)
return;
--
2.25.1
