The previous logic is recording the amount of valid vcn instances
to use them on SRIOV, it is a hard task due to the vcn accessment is
based on the index of the vcn instance.

there is a machanism which recording the invalid instance and skipping
the invalid one, re-use this mechanism on SRIOV environment.

Signed-off-by: Peng Ju Zhou <pengju.z...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 25 +++++++++++++------------
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index c3580de3ea9c..954ab7e76926 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -88,10 +88,10 @@ static int vcn_v3_0_early_init(void *handle)
        int i;
 
        if (amdgpu_sriov_vf(adev)) {
+               adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
                for (i = 0; i < VCN_INSTANCES_SIENNA_CICHLID; i++)
                        if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 
i))
-                               adev->vcn.num_vcn_inst++;
-               adev->vcn.harvest_config = 0;
+                               adev->vcn.harvest_config |= 1 << i;
                adev->vcn.num_enc_rings = 1;
 
        } else {
@@ -151,8 +151,7 @@ static int vcn_v3_0_sw_init(void *handle)
                adev->firmware.fw_size +=
                        ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 
-               if ((adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) ||
-                   (amdgpu_sriov_vf(adev) && adev->asic_type == 
CHIP_SIENNA_CICHLID)) {
+               if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) {
                        adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = 
AMDGPU_UCODE_ID_VCN1;
                        adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = 
adev->vcn.fw;
                        adev->firmware.fw_size +=
@@ -322,17 +321,19 @@ static int vcn_v3_0_hw_init(void *handle)
                                continue;
 
                        ring = &adev->vcn.inst[i].ring_dec;
-                       ring->wptr = 0;
-                       ring->wptr_old = 0;
-                       vcn_v3_0_dec_ring_set_wptr(ring);
-                       ring->sched.ready = true;
+                       if (ring->sched.ready) {
+                               ring->wptr = 0;
+                               ring->wptr_old = 0;
+                               vcn_v3_0_dec_ring_set_wptr(ring);
+                       }
 
                        for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
                                ring = &adev->vcn.inst[i].ring_enc[j];
-                               ring->wptr = 0;
-                               ring->wptr_old = 0;
-                               vcn_v3_0_enc_ring_set_wptr(ring);
-                               ring->sched.ready = true;
+                               if (ring->sched.ready) {
+                                       ring->wptr = 0;
+                                       ring->wptr_old = 0;
+                                       vcn_v3_0_enc_ring_set_wptr(ring);
+                               }
                        }
                }
        } else {
-- 
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Reply via email to