For Aldebaran, driver needs to query DramMegaBaseAddress to
check if DF hashing is enabled.
Signed-off-by: Mukul Joshi <mukul.jo...@amd.com>
Acked-by: Alex Deucher <alexander.deuc...@amd.com>
Reviewed-by: Harish Kasiviswanathan <harish.kasiviswanat...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 9 +++++----
drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h | 3 +++
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
index 36ba229576d8..14514a145c17 100644
--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
@@ -277,13 +277,14 @@ static u32 df_v3_6_get_fb_channel_number(struct
amdgpu_device *adev)
{
u32 tmp;
- tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);
- if (adev->asic_type == CHIP_ALDEBARAN)
+ if (adev->asic_type == CHIP_ALDEBARAN) {
+ tmp = RREG32_SOC15(DF, 0, mmDF_GCM_AON0_DramMegaBaseAddress0);
tmp &=
ALDEBARAN_DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
- else
+ } else {
+ tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);
tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
-
+ }
tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
return tmp;
diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
index bb2c9c7a18df..bd37aa6b6560 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
@@ -33,6 +33,9 @@
#define mmDF_CS_UMC_AON0_DramBaseAddress0
0x0044
#define mmDF_CS_UMC_AON0_DramBaseAddress0_BASE_IDX
0
+#define mmDF_GCM_AON0_DramMegaBaseAddress0
0x0064
+#define mmDF_GCM_AON0_DramMegaBaseAddress0_BASE_IDX
0
+
#define smnPerfMonCtlLo0 0x01d440UL
#define smnPerfMonCtlHi0 0x01d444UL
#define smnPerfMonCtlLo1 0x01d450UL
--
2.17.1
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