From: Michael Strauss <michael.stra...@amd.com>
[Why&How]
Add logs to verify ILR optimization behaviour on boot
Signed-off-by: Michael Strauss <michael.stra...@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlaus...@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pil...@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 9 +++++++--
.../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 ++++
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 79c652eaddb6..4713f09bcbf1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1434,6 +1434,7 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc,
}
if (is_edp_ilr_optimization_required(link, crtc_timing)) {
+ DC_LOG_EVENT_LINK_TRAINING("Seamless boot disabled to optimize
eDP link rate\n");
return false;
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index bbf2865b25c5..3ff3d9e90983 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -4739,8 +4739,10 @@ bool is_edp_ilr_optimization_required(struct dc_link
*link, struct dc_crtc_timin
core_link_read_dpcd(link, DP_LINK_BW_SET,
&link_bw_set, sizeof(link_bw_set));
- if (link_bw_set)
+ if (link_bw_set) {
+ DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required,
VBIOS used link_bw_set\n");
return true;
+ }
// Read DPCD 00115h to find the edp link rate set used
core_link_read_dpcd(link, DP_LINK_RATE_SET,
@@ -4755,9 +4757,12 @@ bool is_edp_ilr_optimization_required(struct dc_link
*link, struct dc_crtc_timin
decide_edp_link_settings(link, &link_setting, req_bw);
if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] !=
link_setting.link_rate ||
- lane_count_set.bits.LANE_COUNT_SET !=
link_setting.lane_count)
+ lane_count_set.bits.LANE_COUNT_SET !=
link_setting.lane_count) {
+ DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required,
VBIOS link_rate_set not optimal\n");
return true;
+ }
+ DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS
set optimal link_rate_set\n");
return false;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index dd903b267ca5..5ddeee96bf23 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1695,6 +1695,8 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct
dc_state *context)
bool can_apply_edp_fast_boot = false;
bool can_apply_seamless_boot = false;
bool keep_edp_vdd_on = false;
+ DC_LOGGER_INIT();
+
get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num);
get_edp_links(dc, edp_links, &edp_num);
@@ -1717,6 +1719,8 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct
dc_state *context)
edp_stream = edp_streams[0];
can_apply_edp_fast_boot =
!is_edp_ilr_optimization_required(edp_stream->link, &edp_stream->timing);
edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot;
+ if (can_apply_edp_fast_boot)
+ DC_LOG_EVENT_LINK_TRAINING("eDP
fast boot disabled to optimize link rate\n");
break;
}
--
2.31.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
