[AMD Public Use]

Reviewed-by: Hawking Zhang <hawking.zh...@amd.com>

Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-boun...@lists.freedesktop.org> On Behalf Of Feifei Xu
Sent: Thursday, April 15, 2021 14:11
To: amd-gfx@lists.freedesktop.org
Cc: Xu, Feifei <feifei...@amd.com>
Subject: [PATCH] drm/amdgpu: use ratelimited print in sdma4 interrupt

dev_*_ratelimited printing will avoid dmesg flush.

Signed-off-by: Feifei Xu <feifei...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 06247ad454b6..1bc5292ebb33 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2218,7 +2218,7 @@ static int sdma_v4_0_print_iv_entry(struct amdgpu_device 
*adev,
 
        instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
        if (instance < 0 || instance >= adev->sdma.num_instances) {
-               dev_err(adev->dev, "sdma instance invalid %d\n", instance);
+               dev_err_ratelimited(adev->dev, "sdma instance invalid %d\n", 
+instance);
                return -EINVAL;
        }
 
@@ -2228,7 +2228,7 @@ static int sdma_v4_0_print_iv_entry(struct amdgpu_device 
*adev,
        memset(&task_info, 0, sizeof(struct amdgpu_task_info));
        amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 
-       dev_info(adev->dev,
+       dev_info_ratelimited(adev->dev,
                   "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u "
                   "pasid:%u, for process %s pid %d thread %s pid %d\n",
                   instance, addr, entry->src_id, entry->ring_id, entry->vmid, 
@@ -2241,7 +2241,7 @@ static int sdma_v4_0_process_vm_hole_irq(struct 
amdgpu_device *adev,
                                              struct amdgpu_irq_src *source,
                                              struct amdgpu_iv_entry *entry)  {
-       dev_err(adev->dev, "MC or SEM address in VM hole\n");
+       dev_err_ratelimited(adev->dev, "MC or SEM address in VM hole\n");
        sdma_v4_0_print_iv_entry(adev, entry);
        return 0;
 }
@@ -2250,7 +2250,8 @@ static int sdma_v4_0_process_doorbell_invalid_irq(struct 
amdgpu_device *adev,
                                              struct amdgpu_irq_src *source,
                                              struct amdgpu_iv_entry *entry)  {
-       dev_err(adev->dev, "SDMA received a doorbell from BIF with byte_enable 
!=0xff\n");
+
+       dev_err_ratelimited(adev->dev, "SDMA received a doorbell from BIF with 
+byte_enable !=0xff\n");
        sdma_v4_0_print_iv_entry(adev, entry);
        return 0;
 }
@@ -2259,7 +2260,7 @@ static int sdma_v4_0_process_pool_timeout_irq(struct 
amdgpu_device *adev,
                                              struct amdgpu_irq_src *source,
                                              struct amdgpu_iv_entry *entry)  {
-       dev_err(adev->dev,
+       dev_err_ratelimited(adev->dev,
                "Polling register/memory timeout executing POLL_REG/MEM with 
finite timer\n");
        sdma_v4_0_print_iv_entry(adev, entry);
        return 0;
@@ -2269,7 +2270,7 @@ static int sdma_v4_0_process_srbm_write_irq(struct 
amdgpu_device *adev,
                                              struct amdgpu_irq_src *source,
                                              struct amdgpu_iv_entry *entry)  {
-       dev_err(adev->dev,
+       dev_err_ratelimited(adev->dev,
                "SDMA gets an Register Write SRBM_WRITE command in 
non-privilege command buffer\n");
        sdma_v4_0_print_iv_entry(adev, entry);
        return 0;
--
2.25.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=04%7C01%7Chawking.zhang%40amd.com%7C9c54e549a4de44a3ea5208d8ffd54f5e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637540638934360168%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=qCg%2Fc9k8Xj6cS4se72CFDCcy6H8WwAciRoS8MKhuoOU%3D&amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Reply via email to