On Thu, Jan 28, 2021 at 10:07 PM Kenneth Feng <kenneth.f...@amd.com> wrote: > > The power limit and clock ragne are different in AC mode and DC mode. > Firmware does the setting after this feature is enabled. > Applied on mobile skus. > > Signed-off-by: Kenneth Feng <kenneth.f...@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com> > --- > drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > index dffdcebc80e1..faddfa9f5642 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > @@ -261,6 +261,9 @@ sienna_cichlid_get_allowed_feature_mask(struct > smu_context *smu, > *(uint64_t *)feature_mask |= > FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT); > } > > + if (smu->dc_controlled_by_gpio) > + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); > + > if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) && adev->asic_type > > CHIP_SIENNA_CICHLID) > *(uint64_t *)feature_mask |= > FEATURE_MASK(FEATURE_GFX_DCS_BIT); > > -- > 2.17.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
