From: Chiawen Huang <chiawen.hu...@amd.com>
[Why]
When switching single pipe to split pipe, the bandwidth check is just
for first pipe. The 2nd pipe with abnormal(or zero) dpp clock when pipe
ready and unlock leads the garbage on display.
[How]
Removed external increasing dpp clock check, the internal function
already loops all of pipes to check whether update dpp clock.
Signed-off-by: Chiawen Huang <chiawen.hu...@amd.com>
Reviewed-by: Tony Cheng <tony.ch...@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.sique...@amd.com>
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index f2114bc910bf..ec9dc265cde0 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -257,8 +257,7 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
if (update_dppclk || update_dispclk)
dcn20_update_clocks_update_dentist(clk_mgr);
// always update dtos unless clock is lowered and not
safe to lower
- if (new_clocks->dppclk_khz >=
dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
- dcn20_update_clocks_update_dpp_dto(clk_mgr,
context, safe_to_lower);
+ dcn20_update_clocks_update_dpp_dto(clk_mgr, context,
safe_to_lower);
}
}
--
2.25.1
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