Re: [PATCH] drm/amdgpu: drop psp ih programming for sriov guest on navi

[Deucher, Alexander]

[AMD Official Use Only - Internal Distribution Only]

Acked-by: Alex Deucher <alexander.deuc...@amd.com>
________________________________
From: amd-gfx <amd-gfx-boun...@lists.freedesktop.org> on behalf of Hawking 
Zhang <hawking.zh...@amd.com>
Sent: Tuesday, December 22, 2020 6:10 AM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Sierra 
Guiza, Alejandro (Alex) <alex.sie...@amd.com>; Jian, Jane <jane.j...@amd.com>
Cc: Zhang, Hawking <hawking.zh...@amd.com>
Subject: [PATCH] drm/amdgpu: drop psp ih programming for sriov guest on navi

the psp access ih path is not needed in navi

Signed-off-by: Hawking Zhang <hawking.zh...@amd.com>
Change-Id: Ib68bfb1b13e1cec03ec27bc9a867e2b37fc2fc8a
---
 drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 18 ++----------------
 1 file changed, 2 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c 
b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 060357625504..f4e4040bbd25 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -151,14 +151,7 @@ static int navi10_ih_toggle_ring_interrupts(struct 
amdgpu_device *adev,
         /* enable_intr field is only valid in ring0 */
         if (ih == &adev->irq.ih)
                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 
: 0));
-       if (amdgpu_sriov_vf(adev)) {
-               if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
-                       dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
-                       return -ETIMEDOUT;
-               }
-       } else {
-               WREG32(ih_regs->ih_rb_cntl, tmp);
-       }
+       WREG32(ih_regs->ih_rb_cntl, tmp);

         if (enable) {
                 ih->enabled = true;
@@ -268,14 +261,7 @@ static int navi10_ih_enable_ring(struct amdgpu_device 
*adev,
                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
         }
-       if (amdgpu_sriov_vf(adev)) {
-               if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
-                       dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
-                       return -ETIMEDOUT;
-               }
-       } else {
-               WREG32(ih_regs->ih_rb_cntl, tmp);
-       }
+       WREG32(ih_regs->ih_rb_cntl, tmp);

         if (ih == &adev->irq.ih) {
                 /* set the ih ring 0 writeback address whether it's enabled or 
not */
--
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=04%7C01%7Calexander.deucher%40amd.com%7C5cf4dad458df44a5212e08d8a66a3f36%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637442322548665184%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=sadpoKT2ULD1eTcp8%2Bd3UCklVDIEji07YXGokQAlkaM%3D&amp;reserved=0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx