[PATCH] drm/amdgpu: Add gfx doorbell setting for Vangogh

[Jinzhou Su]

Using KIQ to map GFX queues instead of MMIO for gfx async ring,
add missing doorbell range setting.

Signed-off-by: Jinzhou.Su <jinzhou...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 24 ++++++++++++++----------
 1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index a6d03931f7fa..9b4e5d53432f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -5995,17 +5995,19 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct 
amdgpu_device *adev,
 {
        u32 tmp;
 
-       tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
-       if (ring->use_doorbell) {
-               tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
-                                   DOORBELL_OFFSET, ring->doorbell_index);
-               tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
-                                   DOORBELL_EN, 1);
-       } else {
-               tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
-                                   DOORBELL_EN, 0);
+       if (!amdgpu_async_gfx_ring) {
+           tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
+           if (ring->use_doorbell) {
+                   tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
+                                       DOORBELL_OFFSET, ring->doorbell_index);
+                   tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
+                                       DOORBELL_EN, 1);
+           } else {
+                   tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
+                                       DOORBELL_EN, 0);
+           }
+           WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
        }
-       WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
@@ -6349,6 +6351,8 @@ static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring 
*ring)
                                    DOORBELL_EN, 0);
        mqd->cp_rb_doorbell_control = tmp;
 
+       /* set doorbell range */
+       gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
        /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
        ring->wptr = 0;
        mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
-- 
2.17.1

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