From: Bhawanpreet Lakha <bhawanpreet.la...@amd.com>
Handle CAVE_DIMGREY_CAVEFISH in amdgpu_dm
v2: fix rebase typo (Alex)
Signed-off-by: Bhawanpreet Lakha <bhawanpreet.la...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 25 ++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 3cf4e08931bb..f45f9baec156 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -104,6 +104,10 @@ MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
#define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_02)
+#define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
+MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
+#endif
#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
@@ -1140,6 +1144,9 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_02)
+ case CHIP_DIMGREY_CAVEFISH:
+#endif
#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
case CHIP_VANGOGH:
#endif
@@ -1255,6 +1262,12 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
break;
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_02)
+ case CHIP_DIMGREY_CAVEFISH:
+ dmub_asic = DMUB_ASIC_DCN302;
+ fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
+ break;
+#endif
default:
/* ASIC doesn't support DMUB. */
@@ -3376,6 +3389,9 @@ static int amdgpu_dm_initialize_drm_device(struct
amdgpu_device *adev)
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_02)
+ case CHIP_DIMGREY_CAVEFISH:
+#endif
#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
case CHIP_VANGOGH:
#endif
@@ -3633,6 +3649,9 @@ static int dm_early_init(void *handle)
break;
#endif
case CHIP_NAVI14:
+#if defined(CONFIG_DRM_AMD_DC_DCN3_02)
+ case CHIP_DIMGREY_CAVEFISH:
+#endif
adev->mode_info.num_crtc = 5;
adev->mode_info.num_hpd = 5;
adev->mode_info.num_dig = 5;
@@ -3952,6 +3971,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
adev->asic_type == CHIP_SIENNA_CICHLID ||
adev->asic_type == CHIP_NAVY_FLOUNDER ||
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_02)
+ adev->asic_type == CHIP_DIMGREY_CAVEFISH ||
+#endif
#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
adev->asic_type == CHIP_VANGOGH ||
#endif
@@ -3976,7 +3998,8 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
if (adev->asic_type == CHIP_SIENNA_CICHLID ||
- adev->asic_type == CHIP_NAVY_FLOUNDER)
+ adev->asic_type == CHIP_NAVY_FLOUNDER ||
+ adev->asic_type == CHIP_DIMGREY_CAVEFISH)
tiling_info->gfx9.num_pkrs =
adev->gfx.config.gb_addr_config_fields.num_pkrs;
#endif
ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
--
2.25.4
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