From: Huang Rui <ray.hu...@amd.com>
This patch is to add GFX10 based APU Van Gogh KFD support. We will treat Van
Gogh as "dgpu" (bypass IOMMU v2).
Signed-off-by: Huang Rui <ray.hu...@amd.com>
Acked-by: Alex Deucher <alexander.deuc...@amd.com>
Reviewed-by: Yong Zhao <yong.z...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 5 +++++
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 20 +++++++++++++++++++
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 1 +
.../gpu/drm/amd/amdkfd/kfd_packet_manager.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 1 +
6 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index d2981524dba0..0eeda7904c14 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -141,6 +141,7 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = {
#define renoir_cache_info carrizo_cache_info
/* TODO - check & update Navi10 cache details */
#define navi10_cache_info carrizo_cache_info
+#define vangogh_cache_info carrizo_cache_info
static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
struct crat_subtype_computeunit *cu)
@@ -683,6 +684,10 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
pcache_info = navi10_cache_info;
num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
break;
+ case CHIP_VANGOGH:
+ pcache_info = vangogh_cache_info;
+ num_of_cache_types = ARRAY_SIZE(vangogh_cache_info);
+ break;
default:
return -EINVAL;
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 903170e59342..81751da79feb 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -76,6 +76,7 @@ static const struct kfd2kgd_calls *kfd2kgd_funcs[] = {
[CHIP_NAVI14] = &gfx_v10_kfd2kgd,
[CHIP_SIENNA_CICHLID] = &gfx_v10_3_kfd2kgd,
[CHIP_NAVY_FLOUNDER] = &gfx_v10_3_kfd2kgd,
+ [CHIP_VANGOGH] = &gfx_v10_3_kfd2kgd,
};
#ifdef KFD_SUPPORT_IOMMU_V2
@@ -498,6 +499,24 @@ static const struct kfd_device_info
navy_flounder_device_info = {
.num_sdma_queues_per_engine = 8,
};
+static const struct kfd_device_info vangogh_device_info = {
+ .asic_family = CHIP_VANGOGH,
+ .asic_name = "vangogh",
+ .max_pasid_bits = 16,
+ .max_no_of_hqd = 24,
+ .doorbell_size = 8,
+ .ih_ring_entry_size = 8 * sizeof(uint32_t),
+ .event_interrupt_class = &event_interrupt_class_v9,
+ .num_of_watch_points = 4,
+ .mqd_size_aligned = MQD_SIZE_ALIGNED,
+ .needs_iommu_device = false,
+ .supports_cwsr = true,
+ .needs_pci_atomics = false,
+ .num_sdma_engines = 1,
+ .num_xgmi_sdma_engines = 0,
+ .num_sdma_queues_per_engine = 2,
+};
+
/* For each entry, [0] is regular and [1] is virtualisation device. */
static const struct kfd_device_info *kfd_supported_devices[][2] = {
#ifdef KFD_SUPPORT_IOMMU_V2
@@ -522,6 +541,7 @@ static const struct kfd_device_info
*kfd_supported_devices[][2] = {
[CHIP_NAVI14] = {&navi14_device_info, NULL},
[CHIP_SIENNA_CICHLID] = {&sienna_cichlid_device_info,
&sienna_cichlid_device_info},
[CHIP_NAVY_FLOUNDER] = {&navy_flounder_device_info,
&navy_flounder_device_info},
+ [CHIP_VANGOGH] = {&vangogh_device_info, NULL},
};
static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 62504d5fa42b..7971bbe696d0 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1925,6 +1925,7 @@ struct device_queue_manager
*device_queue_manager_init(struct kfd_dev *dev)
case CHIP_NAVI14:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
device_queue_manager_init_v10_navi10(&dqm->asic_ops);
break;
default:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
index 3c22909470f2..379457d1b250 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
@@ -417,6 +417,7 @@ int kfd_init_apertures(struct kfd_process *process)
case CHIP_NAVI14:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
kfd_init_apertures_v9(pdd, id);
break;
default:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
index 47ee40fbbd86..9beb2eabd56e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
@@ -247,6 +247,7 @@ int pm_init(struct packet_manager *pm, struct
device_queue_manager *dqm)
case CHIP_NAVI14:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
pm->pmf = &kfd_v9_pm_funcs;
break;
default:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 2b31c3066aaa..da6b493c520f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1375,6 +1375,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
case CHIP_NAVI14:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
--
2.25.4
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