Add xgmi perfmons for Arcturus.

Signed-off-by: Jonathan Kim <jonathan....@amd.com>

v2: Resend for re-review with alignment for v3 in patch 2.
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c | 41 ++++++++++++++++++++++++-
 drivers/gpu/drm/amd/amdgpu/df_v3_6.c    |  3 ++
 2 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
index 74fe8fbdc0d1..c58af4495c5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
@@ -34,6 +34,8 @@
 #define NUM_EVENTS_DF_LEGACY           8
 #define NUM_EVENTS_VEGA20_XGMI         2
 #define NUM_EVENTS_VEGA20_MAX          NUM_EVENTS_VEGA20_XGMI
+#define NUM_EVENTS_ARCTURUS_XGMI       6
+#define NUM_EVENTS_ARCTURUS_MAX                NUM_EVENTS_ARCTURUS_XGMI
 
 struct amdgpu_pmu_event_attribute {
        struct device_attribute attr;
@@ -98,6 +100,16 @@ static const char *vega20_events[NUM_EVENTS_VEGA20_MAX][2] 
= {
        { "xgmi_link1_data_outbound", "event=0x7,instance=0x47,umask=0x2" }
 };
 
+/* Arcturus events */
+static const char *arcturus_events[NUM_EVENTS_ARCTURUS_MAX][2] = {
+       { "xgmi_link0_data_outbound", "event=0x7,instance=0x4b,umask=0x2" },
+       { "xgmi_link1_data_outbound", "event=0x7,instance=0x4c,umask=0x2" },
+       { "xgmi_link2_data_outbound", "event=0x7,instance=0x4d,umask=0x2" },
+       { "xgmi_link3_data_outbound", "event=0x7,instance=0x4e,umask=0x2" },
+       { "xgmi_link4_data_outbound", "event=0x7,instance=0x4f,umask=0x2" },
+       { "xgmi_link5_data_outbound", "event=0x7,instance=0x50,umask=0x2" }
+};
+
 /* All df_vega20_* items are DEPRECATED. Use vega20_ items above instead. */
 static const char *df_vega20_formats[NUM_FORMATS_DF_LEGACY][2] = {
        { "event", "config:0-7" },
@@ -413,6 +425,32 @@ static int init_pmu_by_type(struct amdgpu_pmu_entry 
*pmu_entry,
 
                /* other events can be added here */
 
+               break;
+       case CHIP_ARCTURUS:
+               ret = amdgpu_pmu_alloc_pmu_attrs(&pmu_entry->fmt_attr_group,
+                                               &pmu_entry->fmt_attr,
+                                               NUM_FORMATS_AMDGPU_PMU,
+                                               &pmu_entry->evt_attr_group,
+                                               &pmu_entry->evt_attr,
+                                               NUM_EVENTS_ARCTURUS_MAX);
+
+               if (ret)
+                       goto err_out;
+
+               amdgpu_pmu_create_attributes(&pmu_entry->fmt_attr_group,
+                                               pmu_entry->fmt_attr,
+                                               amdgpu_pmu_formats,
+                                               0, NUM_FORMATS_AMDGPU_PMU, 0);
+
+               amdgpu_pmu_create_attributes(&pmu_entry->evt_attr_group,
+                                               pmu_entry->evt_attr,
+                                               arcturus_events,
+                                               0, NUM_EVENTS_ARCTURUS_XGMI,
+                                               PERF_TYPE_AMDGPU_XGMI);
+               num_events += NUM_EVENTS_ARCTURUS_XGMI;
+
+               /* other events can be added here */
+
                break;
        default:
                ret = -ENODEV;
@@ -473,7 +511,8 @@ void amdgpu_pmu_fini(struct amdgpu_device *adev)
 
 static bool amdgpu_pmu_is_supported(struct amdgpu_device *adev)
 {
-       return adev->asic_type == CHIP_VEGA20;
+       return adev->asic_type == CHIP_VEGA20 ||
+               adev->asic_type == CHIP_ARCTURUS;
 }
 
 /* init amdgpu_pmu */
diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c 
b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
index 6e57ae95f997..6b4b30a8dce5 100644
--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
@@ -513,6 +513,7 @@ static int df_v3_6_pmc_start(struct amdgpu_device *adev, 
uint64_t config,
 
        switch (adev->asic_type) {
        case CHIP_VEGA20:
+       case CHIP_ARCTURUS:
                if (is_add)
                        return df_v3_6_pmc_add_cntr(adev, config);
 
@@ -554,6 +555,7 @@ static int df_v3_6_pmc_stop(struct amdgpu_device *adev, 
uint64_t config,
 
        switch (adev->asic_type) {
        case CHIP_VEGA20:
+       case CHIP_ARCTURUS:
                ret = df_v3_6_pmc_get_ctrl_settings(adev,
                        config,
                        counter_idx,
@@ -590,6 +592,7 @@ static void df_v3_6_pmc_get_count(struct amdgpu_device 
*adev,
 
        switch (adev->asic_type) {
        case CHIP_VEGA20:
+       case CHIP_ARCTURUS:
                df_v3_6_pmc_get_read_settings(adev, config, counter_idx,
                                                &lo_base_addr, &hi_base_addr);
 
-- 
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Reply via email to