[PATCH 4/5] drm/amd/pm: add Sienna Cichlid deep sleep control interface

[Evan Quan]

This is needed for UMD pstate switch.

Change-Id: I97ee3af60f4a3e4c2f575ce8c8e1a2866ed37f02
Signed-off-by: Evan Quan <evan.q...@amd.com>
---
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 34 +++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 45b9defebd07..b2ad6a5f6728 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -2718,6 +2718,39 @@ static int sienna_cichlid_enable_mgpu_fan_boost(struct 
smu_context *smu)
                                               NULL);
 }
 
+static int sienna_cichlid_deep_sleep_control(struct smu_context *smu,
+                                            bool enablement)
+{
+       struct amdgpu_device *adev = smu->adev;
+       int ret = 0;
+
+       if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
+               ret = smu_cmn_feature_set_enabled(smu, 
SMU_FEATURE_DS_GFXCLK_BIT, enablement);
+               if (ret) {
+                       dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", 
enablement ? "enable" : "disable");
+                       return ret;
+               }
+       }
+
+       if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
+               ret = smu_cmn_feature_set_enabled(smu, 
SMU_FEATURE_DS_SOCCLK_BIT, enablement);
+               if (ret) {
+                       dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", 
enablement ? "enable" : "disable");
+                       return ret;
+               }
+       }
+
+       if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
+               ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, 
enablement);
+               if (ret) {
+                       dev_err(adev->dev, "Failed to %s LCLK DS!\n", 
enablement ? "enable" : "disable");
+                       return ret;
+               }
+       }
+
+       return ret;
+}
+
 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
        .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
        .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
@@ -2797,6 +2830,7 @@ static const struct pptable_funcs 
sienna_cichlid_ppt_funcs = {
        .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
        .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
        .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
+       .deep_sleep_control = sienna_cichlid_deep_sleep_control,
 };
 
 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
-- 
2.28.0

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