Reviewed-by: Rodrigo Siqueira <rodrigo.sique...@amd.com> On 08/14, Bhawanpreet Lakha wrote: > This field is not defined for DCN3 > > Signed-off-by: Bhawanpreet Lakha <bhawanpreet.la...@amd.com> > --- > .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h | 1 + > .../include/asic_reg/dcn/dcn_3_0_0_sh_mask.h | 22 +++++++++++++++++++ > 2 files changed, 23 insertions(+) > > diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h > b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h > index 667640c4b288..1118e33aaa2c 100644 > --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h > +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h > @@ -94,6 +94,7 @@ > DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_CLOCK_EN, mask_sh), \ > DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DISPCLK_R_GATE_DIS, mask_sh), \ > DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DSCCLK_R_GATE_DIS, mask_sh), \ > + DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_DBG_EN, mask_sh), \ > DSC_SF(DSCC0_DSCC_CONFIG0, ICH_RESET_AT_END_OF_LINE, mask_sh), \ > DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_PER_LINE, mask_sh), \ > DSC_SF(DSCC0_DSCC_CONFIG0, ALTERNATE_ICH_ENCODING_EN, mask_sh), \ > diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h > b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h > index 0e0319e98c07..ea683f452bb3 100755 > --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h > @@ -50271,6 +50271,10 @@ > #define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK > 0x00000001L > #define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK > 0x00000010L > #define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK > 0x00000100L > +//DSC_TOP0_DSC_DEBUG_CONTROL > +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT > 0x0 > +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK > 0x00000001L > + > > // addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec > //DSCCIF0_DSCCIF_CONFIG0 > @@ -50789,6 +50793,9 @@ > #define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK > 0x00000001L > #define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK > 0x00000010L > #define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK > 0x00000100L > +//DSC_TOP1_DSC_DEBUG_CONTROL > +#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT > 0x0 > +#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK > 0x00000001L > > > // addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec > @@ -51308,6 +51315,10 @@ > #define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK > 0x00000001L > #define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK > 0x00000010L > #define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK > 0x00000100L > +//DSC_TOP2_DSC_DEBUG_CONTROL > +#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT > 0x0 > +#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK > 0x00000001L > + > > // addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec > //DSCCIF2_DSCCIF_CONFIG0 > @@ -51826,6 +51837,9 @@ > #define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK > 0x00000001L > #define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK > 0x00000010L > #define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK > 0x00000100L > +//DSC_TOP3_DSC_DEBUG_CONTROL > +#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT > 0x0 > +#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK > 0x00000001L > > > // addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec > @@ -52346,6 +52360,10 @@ > #define DSC_TOP4_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK > 0x00000001L > #define DSC_TOP4_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK > 0x00000010L > #define DSC_TOP4_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK > 0x00000100L > +//DSC_TOP4_DSC_DEBUG_CONTROL > +#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT > 0x0 > +#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK > 0x00000001L > + > > // addressBlock: dce_dc_dsc4_dispdec_dsccif_dispdec > //DSCCIF4_DSCCIF_CONFIG0 > @@ -52864,6 +52882,10 @@ > #define DSC_TOP5_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK > 0x00000001L > #define DSC_TOP5_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK > 0x00000010L > #define DSC_TOP5_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK > 0x00000100L > +//DSC_TOP5_DSC_DEBUG_CONTROL > +#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT > 0x0 > +#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK > 0x00000001L > + > > // addressBlock: dce_dc_dsc5_dispdec_dsccif_dispdec > //DSCCIF5_DSCCIF_CONFIG0 > -- > 2.17.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7CRodrigo.Siqueira%40amd.com%7Cc6285b82567b4565541d08d840731e6b%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637330210522549360&sdata=PqUidLq7uHZZAw%2B78gvJ6jsnG1pmL5ywo5fT8u3A060%3D&reserved=0
-- Rodrigo Siqueira https://siqueira.tech
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