The series expect patch2 and pach6 are reviewed-by: Evan Quan
<evan.q...@amd.com>
-----Original Message-----
From: Liang, Prike <prike.li...@amd.com>
Sent: Thursday, September 26, 2019 11:50 AM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan <evan.q...@amd.com>; keneth.f...@amd.com; Huang, Ray
<ray.hu...@amd.com>; Liang, Prike <prike.li...@amd.com>
Subject: [PATCH 8/8] drm/amd/powerplay: update the interface for getting dpm
full scale clock frequency
Update get_dpm_uclk_limited to get more clock type full scale dpm frequency.
Signed-off-by: Prike Liang <prike.li...@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 7 ++++---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 16 ++++++---------
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 28 ++++++++++++++++++++++----
3 files changed, 34 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index b118863..eb81edd 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -465,7 +465,8 @@ struct pptable_funcs {
int (*display_disable_memory_clock_switch)(struct smu_context *smu,
bool disable_memory_clock_switch);
void (*dump_pptable)(struct smu_context *smu);
int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool
asic_default);
- int (*get_dpm_uclk_limited)(struct smu_context *smu, uint32_t *clock,
bool max);
+ int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type
clk_type,
+ uint32_t dpm_level, uint32_t *freq);
};
struct smu_funcs
@@ -774,8 +775,8 @@ struct smu_funcs
((smu)->ppt_funcs->set_performance_level?
(smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL); #define
smu_dump_pptable(smu) \
((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs->dump_pptable((smu))
: 0) -#define smu_get_dpm_uclk_limited(smu, clock, max) \
- ((smu)->ppt_funcs->get_dpm_uclk_limited ?
(smu)->ppt_funcs->get_dpm_uclk_limited((smu), (clock), (max)) : -EINVAL)
+#define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq) \
+ ((smu)->ppt_funcs->get_dpm_clk_limited ?
+(smu)->ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level),
+(freq)) : -EINVAL)
#define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
((smu)->funcs->set_soft_freq_limited_range ?
(smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) :
-EINVAL) diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index c63518a..556ca68 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -161,21 +161,17 @@ static int renoir_tables_init(struct smu_context *smu,
struct smu_table *tables)
* This interface just for getting uclk ultimate freq and should't introduce
* other likewise function result in overmuch callback.
*/
-static int renoir_get_dpm_uclk_limited(struct smu_context *smu, uint32_t
*clock, bool max)
+static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum
smu_clk_type clk_type,
+ uint32_t dpm_level, uint32_t
*freq)
{
+ DpmClocks_t *clk_table = smu->smu_table.clocks_table;
- DpmClocks_t *table = smu->smu_table.clocks_table;
-
- if (!clock || !table)
+ if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
- if (max)
- *clock = table->FClocks[NUM_FCLK_DPM_LEVELS-1].Freq;
- else
- *clock = table->FClocks[0].Freq;
+ GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq);
return 0;
-
}
static int renoir_print_clk_levels(struct smu_context *smu, @@ -555,7 +551,7
@@ static const struct pptable_funcs renoir_ppt_funcs = {
.get_smu_table_index = renoir_get_smu_table_index,
.tables_init = renoir_tables_init,
.set_power_state = NULL,
- .get_dpm_uclk_limited = renoir_get_dpm_uclk_limited,
+ .get_dpm_clk_limited = renoir_get_dpm_clk_limited,
.print_clk_levels = renoir_print_clk_levels,
.get_current_power_state = renoir_get_current_power_state,
.dpm_set_uvd_enable = renoir_dpm_set_uvd_enable, diff --git
a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index c0c0a60..c78c69d 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -323,10 +323,18 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct
smu_context *smu, enum smu_clk
uint32_t *min, uint32_t *max)
{
int ret = 0;
+ uint32_t mclk_mask, soc_mask;
mutex_lock(&smu->mutex);
if (max) {
+ ret = smu_get_profiling_clk_mask(smu,
AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
+ NULL,
+ &mclk_mask,
+ &soc_mask);
+ if (ret)
+ goto failed;
+
switch (clk_type) {
case SMU_GFXCLK:
case SMU_SCLK:
@@ -340,14 +348,20 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct
smu_context *smu, enum smu_clk
goto failed;
break;
case SMU_UCLK:
- ret = smu_get_dpm_uclk_limited(smu, max, true);
+ case SMU_FCLK:
+ case SMU_MCLK:
+ ret = smu_get_dpm_clk_limited(smu, clk_type, mclk_mask,
max);
+ if (ret)
+ goto failed;
+ break;
+ case SMU_SOCCLK:
+ ret = smu_get_dpm_clk_limited(smu, clk_type, soc_mask,
max);
if (ret)
goto failed;
break;
default:
ret = -EINVAL;
goto failed;
-
}
}
@@ -365,7 +379,14 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct
smu_context *smu, enum smu_clk
goto failed;
break;
case SMU_UCLK:
- ret = smu_get_dpm_uclk_limited(smu, min, false);
+ case SMU_FCLK:
+ case SMU_MCLK:
+ ret = smu_get_dpm_clk_limited(smu, clk_type, 0, min);
+ if (ret)
+ goto failed;
+ break;
+ case SMU_SOCCLK:
+ ret = smu_get_dpm_clk_limited(smu, clk_type, 0, min);
if (ret)
goto failed;
break;
@@ -373,7 +394,6 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct
smu_context *smu, enum smu_clk
ret = -EINVAL;
goto failed;
}
-
}
failed:
mutex_unlock(&smu->mutex);
--
2.7.4
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