The new memory mapping scheme is:
For vram:
Fine-grain coherency: local CC and remote UC, with snoop.
Coarse-grain coherency: local RW and remote UC, with snoop.
For host memory (not changed)
Fine-grain coherency: UC
Coarse-grain coherency: NC
Change-Id: I6a071249f953cbed813bfd953b6a2e0826f54f86
Signed-off-by: Oak Zeng <oak.z...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 47 ++++++++++++++++++++++++++++++++++-
2 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 2b2af6a..51dae7f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -420,6 +420,7 @@ static uint32_t gmc_v6_0_get_vm_mapping_flags(struct
amdgpu_device *adev,
return mapping_flags;
}
+
static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
bool value)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 8faead3..2f742e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -646,6 +646,35 @@ static uint32_t gmc_v9_0_get_vm_mapping_flags(struct
amdgpu_device *adev,
return mapping_flags;
}
+static uint32_t gmc_v9_0_arcturus_get_vm_mapping_flags(struct amdgpu_device
*adev,
+ uint32_t alloc_flags, bool remote_mapping)
+{
+ uint32_t mapping_flags = AMDGPU_VM_PAGE_READABLE;
+
+ if (alloc_flags & ALLOC_MEM_FLAGS_WRITABLE)
+ mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
+ if (alloc_flags & ALLOC_MEM_FLAGS_EXECUTABLE)
+ mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
+
+ if ((alloc_flags & ALLOC_MEM_FLAGS_VRAM)) {
+ if (!remote_mapping) {
+ if (alloc_flags & ALLOC_MEM_FLAGS_COHERENT)
+ mapping_flags |= AMDGPU_VM_MTYPE_CC;
+ else
+ mapping_flags |= AMDGPU_VM_MTYPE_RW;
+ } else {
+ mapping_flags |= AMDGPU_VM_MTYPE_UC;
+ mapping_flags |= AMDGPU_VM_PAGE_INVALIDATE_PROBE;
+ }
+ } else {
+ if (alloc_flags & ALLOC_MEM_FLAGS_COHERENT)
+ mapping_flags |= AMDGPU_VM_MTYPE_UC;
+ else
+ mapping_flags |= AMDGPU_VM_MTYPE_NC;
+ }
+
+ return mapping_flags;
+}
static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
.flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
@@ -656,9 +685,25 @@ static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
.get_vm_mapping_flags = gmc_v9_0_get_vm_mapping_flags
};
+static const struct amdgpu_gmc_funcs gmc_v9_0_arcturus_gmc_funcs = {
+ .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
+ .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
+ .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
+ .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
+ .get_vm_pde = gmc_v9_0_get_vm_pde,
+ .get_vm_mapping_flags = gmc_v9_0_arcturus_get_vm_mapping_flags
+};
+
static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
{
- adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
+ switch(adev->asic_type) {
+ case CHIP_ARCTURUS:
+ adev->gmc.gmc_funcs = &gmc_v9_0_arcturus_gmc_funcs;
+ break;
+ default:
+ adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
+ break;
+ }
}
static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
--
2.7.4
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