On 2019-07-25 2:15 p.m., Thai, Thong wrote:
> Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This
> bit was previously set by the RBC HW on older firmware. Newer firmware
> uses a SW RBC and this bit has to be set by the driver.
>
> Signed-off-by: Thong Thai <thong.t...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 12 ++++++------
> 2 files changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> index 5e2453ee6b29..4d3bf4adf1eb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> @@ -30,6 +30,7 @@
> #define AMDGPU_VCN_FIRMWARE_OFFSET 256
> #define AMDGPU_VCN_MAX_ENC_RINGS 3
>
> +#define VCN_DEC_KMD_CMD 0x80000000
Please get this line aligned with others, with that fixed, the patch is
Reviewed-by: Leo Liu <leo....@amd.com>
> #define VCN_DEC_CMD_FENCE 0x00000000
> #define VCN_DEC_CMD_TRAP 0x00000001
> #define VCN_DEC_CMD_WRITE_REG 0x00000004
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index bc9726787c97..7091aef95ff0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -1488,7 +1488,7 @@ static void vcn_v2_0_dec_ring_insert_start(struct
> amdgpu_ring *ring)
> amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET,
> 0));
> amdgpu_ring_write(ring, 0);
> amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET,
> 0));
> - amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
> + amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START <<
> 1));
> }
>
> /**
> @@ -1501,7 +1501,7 @@ static void vcn_v2_0_dec_ring_insert_start(struct
> amdgpu_ring *ring)
> static void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
> {
> amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET,
> 0));
> - amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
> + amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END <<
> 1));
> }
>
> /**
> @@ -1546,7 +1546,7 @@ static void vcn_v2_0_dec_ring_emit_fence(struct
> amdgpu_ring *ring, u64 addr, u64
> amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
>
> amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET,
> 0));
> - amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
> + amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));
>
> amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET,
> 0));
> amdgpu_ring_write(ring, 0);
> @@ -1556,7 +1556,7 @@ static void vcn_v2_0_dec_ring_emit_fence(struct
> amdgpu_ring *ring, u64 addr, u64
>
> amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET,
> 0));
>
> - amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
> + amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));
> }
>
> /**
> @@ -1600,7 +1600,7 @@ static void vcn_v2_0_dec_ring_emit_reg_wait(struct
> amdgpu_ring *ring,
>
> amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET,
> 0));
>
> - amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
> + amdgpu_ring_write(ring, VCN_DEC_KMD_CMD |
> (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));
> }
>
> static void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
> @@ -1629,7 +1629,7 @@ static void vcn_v2_0_dec_ring_emit_wreg(struct
> amdgpu_ring *ring,
>
> amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET,
> 0));
>
> - amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
> + amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));
> }
>
> /**
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