Thanks. I'll push both patches with emit_ib_size updated for this patch.
Marek
On Thu, Jun 27, 2019 at 3:50 AM zhoucm1 <zhou...@amd.com> wrote:
> any reason for not care .emit_ib_size in this one?
>
> -David
>
>
> On 2019年06月27日 06:35, Marek Olšák wrote:
> > From: Marek Olšák <marek.ol...@amd.com>
> >
> > Signed-off-by: Marek Olšák <marek.ol...@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 17 +++++++++++++++++
> > 1 file changed, 17 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > index 6baaa65a1daa..5b807a19bbbf 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > @@ -4257,20 +4257,36 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct
> amdgpu_ring *ring,
> > }
> >
> > static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
> > struct amdgpu_job *job,
> > struct amdgpu_ib *ib,
> > uint32_t flags)
> > {
> > unsigned vmid = AMDGPU_JOB_GET_VMID(job);
> > u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
> >
> > + /* Currently, there is a high possibility to get wave ID mismatch
> > + * between ME and GDS, leading to a hw deadlock, because ME
> generates
> > + * different wave IDs than the GDS expects. This situation happens
> > + * randomly when at least 5 compute pipes use GDS ordered append.
> > + * The wave IDs generated by ME are also wrong after
> suspend/resume.
> > + * Those are probably bugs somewhere else in the kernel driver.
> > + *
> > + * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME
> and
> > + * GDS to 0 for this ring (me/pipe).
> > + */
> > + if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
> > + amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG,
> 1));
> > + amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
> > + amdgpu_ring_write(ring,
> ring->adev->gds.gds_compute_max_wave_id);
> > + }
> > +
> > amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
> > BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
> > amdgpu_ring_write(ring,
> > #ifdef __BIG_ENDIAN
> > (2 << 0) |
> > #endif
> > lower_32_bits(ib->gpu_addr));
> > amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
> > amdgpu_ring_write(ring, control);
> > }
> > @@ -5103,20 +5119,21 @@ static void gfx_v10_0_set_rlc_funcs(struct
> amdgpu_device *adev)
> > }
> > }
> >
> > static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
> > {
> > /* init asic gds info */
> > switch (adev->asic_type) {
> > case CHIP_NAVI10:
> > default:
> > adev->gds.gds_size = 0x10000;
> > + adev->gds.gds_compute_max_wave_id = 0x4ff;
> > adev->gds.vgt_gs_max_wave_id = 0x3ff;
> > break;
> > }
> >
> > adev->gds.gws_size = 64;
> > adev->gds.oa_size = 16;
> > }
> >
> > static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct
> amdgpu_device *adev,
> > u32 bitmap)
>
>
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