On Sun, Nov 18, 2018 at 11:12 PM Monk Liu <monk....@amd.com> wrote:
>
> there is a hw issue that disallow us to use strong
> BURST_WRITE for SDMA0/1 engines, without force
> BURST_WRITE field set to 0x1 (64B) we will hit
> h/w bug during stress MMHUB transist
>
> Signed-off-by: Monk Liu <monk....@amd.com>
Acked-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index f4490cd..71404ee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -78,7 +78,7 @@ static const struct soc15_reg_golden
> golden_settings_sdma_4[] = {
> SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL,
> 0x0000fff0, 0x00403000),
> SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff,
> 0x000003c0),
> SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000,
> 0x00000000),
> - SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07,
> 0x02831f07),
> + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07,
> 0x02831d07),
> SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff,
> 0x3f000100),
> SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100,
> 0x00000100),
> SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL,
> 0x0000fff0, 0x00403000),
> --
> 2.7.4
>
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