the cond_exec is needed by sdma mid command buffer
preemption
Signed-off-by: Rex Zhu <[email protected]>
---
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 31 +++++++++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 28 ++++++++++++++++++++++++++++
2 files changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 9a892f8..8bfc68d 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -500,6 +500,34 @@ static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring
*ring, u64 addr, u64 se
amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
}
+static unsigned sdma_v3_0_ring_init_cond_exec(struct amdgpu_ring *ring)
+{
+ unsigned ret;
+
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
+ amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
+ amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
+ amdgpu_ring_write(ring, 1);
+ ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch
later */
+ amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it
later */
+ return ret;
+}
+
+static void sdma_v3_0_ring_patch_cond_exec(struct amdgpu_ring *ring, unsigned
offset)
+{
+ unsigned cur;
+
+ BUG_ON(offset > ring->buf_mask);
+ BUG_ON(ring->ring[offset] != 0x55aa55aa);
+
+ cur = ring->wptr - 1;
+ if (likely(cur > offset))
+ ring->ring[offset] = cur - offset;
+ else
+ ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
+}
+
+
/**
* sdma_v3_0_gfx_stop - stop the gfx async dma engines
*
@@ -1597,6 +1625,7 @@ static void sdma_v3_0_get_clockgating_state(void *handle,
u32 *flags)
.get_wptr = sdma_v3_0_ring_get_wptr,
.set_wptr = sdma_v3_0_ring_set_wptr,
.emit_frame_size =
+ 5 + /* sdma_v3_0_ring_init_cond_exec */
6 + /* sdma_v3_0_ring_emit_hdp_flush */
3 + /* hdp invalidate */
6 + /* sdma_v3_0_ring_emit_pipeline_sync */
@@ -1613,6 +1642,8 @@ static void sdma_v3_0_get_clockgating_state(void *handle,
u32 *flags)
.insert_nop = sdma_v3_0_ring_insert_nop,
.pad_ib = sdma_v3_0_ring_pad_ib,
.emit_wreg = sdma_v3_0_ring_emit_wreg,
+ .init_cond_exec = sdma_v3_0_ring_init_cond_exec,
+ .patch_cond_exec = sdma_v3_0_ring_patch_cond_exec,
};
static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 51e1d1a..64fa6be 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -609,6 +609,31 @@ static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring
*ring, u64 addr, u64 se
amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
}
+static unsigned sdma_v4_0_ring_init_cond_exec(struct amdgpu_ring *ring)
+{
+ unsigned ret;
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
+ amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
+ amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
+ amdgpu_ring_write(ring, 1);
+ ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch
later */
+ amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it
later */
+ return ret;
+}
+
+static void sdma_v4_0_ring_patch_cond_exec(struct amdgpu_ring *ring, unsigned
offset)
+{
+ unsigned cur;
+
+ BUG_ON(offset > ring->buf_mask);
+ BUG_ON(ring->ring[offset] != 0x55aa55aa);
+
+ cur = ring->wptr - 1;
+ if (likely(cur > offset))
+ ring->ring[offset] = cur - offset;
+ else
+ ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
+}
/**
* sdma_v4_0_gfx_stop - stop the gfx async dma engines
@@ -1933,6 +1958,7 @@ static void sdma_v4_0_get_clockgating_state(void *handle,
u32 *flags)
.get_wptr = sdma_v4_0_ring_get_wptr,
.set_wptr = sdma_v4_0_ring_set_wptr,
.emit_frame_size =
+ 5 + /* sdma_v4_0_ring_init_cond_exec */
6 + /* sdma_v4_0_ring_emit_hdp_flush */
3 + /* hdp invalidate */
6 + /* sdma_v4_0_ring_emit_pipeline_sync */
@@ -1953,6 +1979,8 @@ static void sdma_v4_0_get_clockgating_state(void *handle,
u32 *flags)
.emit_wreg = sdma_v4_0_ring_emit_wreg,
.emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+ .init_cond_exec = sdma_v4_0_ring_init_cond_exec,
+ .patch_cond_exec = sdma_v4_0_ring_patch_cond_exec,
};
static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
--
1.9.1
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