Am 28.08.2018 um 06:21 schrieb zhoucm1:
On 2018年08月28日 03:03, Felix Kuehling wrote:
The point of this series seems to be to allow access to small system
memory BOs (one page) without a GART mapping. I'm guessing that reduces
pressure on the GART and removes the need for HDP and TLB flushes.
I think if adding these explain/reason to comments are better to
enable AGP apperture. If that's true, it's really a clever idea.
Well that is one use case. Another one is that we can enable dGPU
without any VRAM.
That is really important for emulation and early ASIC testing.
Regards,
David Zhou
Why
does Patch 10 only enable that on GFXv9? Is there less benefit on older
chips?
Can easily be enabled on older chips as well, but I haven't yet had time
to test it.
Is this related to your recent changes to allow page tables in system
memory?
Yes, as it turned out that otherwise results in a huge bunch of extra
GART mappings.
Regards,
Christian.
See my replies to patch 6 and 8. Other than that, the series is
Acked-by: Felix Kuehling <felix.kuehl...@amd.com>
Regards,
Felix
On 2018-08-27 12:53 PM, Christian König wrote:
Only use the lower address space on GMC9 for the system domain.
Otherwise we would need to sign extend GMC addresses.
Signed-off-by: Christian König <christian.koe...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index e44b5191735d..d982956c8329 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle)
if (r)
return r;
- /* Set the internal MC address mask
- * This is the max address of the GPU's
- * internal address space.
+ /* Use only the lower range for the internal MC address mask.
This is
+ * the max address of the GPU's internal address space.
*/
- adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
+ adev->gmc.mc_mask = 0x7fffffffffffULL;
/* set DMA mask + need_dma32 flags.
* PCIE - can handle 44-bits.
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