There is no need for gpu full access for suspend phase1
because under virtualization there is no hw register access
for dce block.
Change-Id: Ie1154e2065182ba968732af87f866f11141a102b
Signed-off-by: Yintian Tao <yt...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index d84ac23..5da20b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1968,9 +1968,6 @@ static int amdgpu_device_ip_suspend_phase1(struct
amdgpu_device *adev)
{
int i, r;
- if (amdgpu_sriov_vf(adev))
- amdgpu_virt_request_full_gpu(adev, false);
-
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
if (!adev->ip_blocks[i].status.valid)
continue;
@@ -1995,9 +1992,6 @@ static int amdgpu_device_ip_suspend_phase1(struct
amdgpu_device *adev)
}
}
- if (amdgpu_sriov_vf(adev))
- amdgpu_virt_release_full_gpu(adev, false);
-
return 0;
}
--
2.7.4
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