As more hw ip pg feature have been enabled(especial gfx off),
so need to check the hw power state before read/write registers
through mmio.

Signed-off-by: Rex Zhu <rex....@amd.com>
---
 drivers/gpu/drm/amd/include/kgd_pp_interface.h |  1 +
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 21 +++++++++++++++++++++
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h      |  1 +
 3 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 6a41b81..3b5b2de 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -269,6 +269,7 @@ struct amd_pm_funcs {
        int (*get_display_mode_validation_clocks)(void *handle,
                struct amd_pp_simple_clock_info *clocks);
        int (*notify_smu_enable_pwe)(void *handle);
+       bool (*is_hw_ip_on)(void *handle, enum amd_ip_block_type client);
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index da4ebff..c50164e 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1243,6 +1243,26 @@ static int pp_notify_smu_enable_pwe(void *handle)
        return 0;
 }
 
+static bool pp_is_hw_ip_on(void *handle, enum amd_ip_block_type client)
+{
+       struct pp_hwmgr *hwmgr = handle;
+       bool ret;
+
+       if (!hwmgr || !hwmgr->pm_en)
+               return true;
+
+       if (hwmgr->hwmgr_func->is_hw_ip_on == NULL) {
+               pr_info("%s was not implemented.\n", __func__);
+               return true;
+       }
+
+       mutex_lock(&hwmgr->smu_lock);
+       ret = hwmgr->hwmgr_func->is_hw_ip_on(hwmgr, client);
+       mutex_unlock(&hwmgr->smu_lock);
+
+       return ret;
+}
+
 static const struct amd_pm_funcs pp_dpm_funcs = {
        .load_firmware = pp_dpm_load_fw,
        .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
@@ -1274,6 +1294,7 @@ static int pp_notify_smu_enable_pwe(void *handle)
        .odn_edit_dpm_table = pp_odn_edit_dpm_table,
        .set_power_limit = pp_set_power_limit,
        .get_power_limit = pp_get_power_limit,
+       .is_hw_ip_on = pp_is_hw_ip_on,
 /* export to DC */
        .get_sclk = pp_dpm_get_sclk,
        .get_mclk = pp_dpm_get_mclk,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 88f4517..3aca3a3 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -328,6 +328,7 @@ struct pp_hwmgr_func {
        int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
        int (*powergate_mmhub)(struct pp_hwmgr *hwmgr);
        int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr);
+       bool (*is_hw_ip_on)(struct pp_hwmgr *hwmgr, enum amd_ip_block_type 
client);
 };
 
 struct pp_table_func {
-- 
1.9.1

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