From: Boyuan Zhang <boyuan.zh...@amd.com>
Add new mask for enabling system interrupt for jrbc.
Signed-off-by: Boyuan Zhang <boyuan.zh...@amd.com>
---
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
index d6ba269..124383d 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
@@ -982,6 +982,8 @@
#define UVD_MASTINT_EN__VCPU_EN_MASK
0x00000002L
#define UVD_MASTINT_EN__SYS_EN_MASK
0x00000004L
#define UVD_MASTINT_EN__INT_OVERRUN_MASK
0x007FFFF0L
+//UVD_SYS_INT_EN
+#define UVD_SYS_INT_EN__UVD_JRBC_EN_MASK
0x00000010L
//JPEG_CGC_CTRL
#define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT
0x0
#define JPEG_CGC_CTRL__JPEG2_MODE__SHIFT
0x1
--
2.7.4
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