From: Roman Li <[email protected]>

Remove unused legacy tiling format support from dml2.
Legacy asics don't use dml2.

Fixes: 66715fc0ecfd ("drm/amd/display: Sync dcn42 with DC 3.2.373")

Reviewed-by: Leo Li <[email protected]>
Signed-off-by: Roman Li <[email protected]>
---
 .../dml21/inc/dml_top_display_cfg_types.h     | 14 ----
 .../dml21/src/dml2_core/dml2_core_utils.c     | 64 +------------------
 .../dml21/src/dml2_core/dml2_core_utils.h     |  2 -
 3 files changed, 2 insertions(+), 78 deletions(-)

diff --git 
a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h 
b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h
index 4e9abe1a568d..79dfba54344c 100644
--- 
a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h
+++ 
b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h
@@ -26,20 +26,6 @@ enum dml2_swizzle_mode {
        dml2_gfx11_sw_64kb_r_x,
        dml2_gfx11_sw_256kb_d_x,
        dml2_gfx11_sw_256kb_r_x,
-
-       dml2_sw_linear_256b, // GFX10 SW_LINEAR only accepts 256 byte aligned 
pitch
-       dml2_gfx10_sw_64kb_r_x,
-       dml2_gfx102_sw_64kb_s,
-       dml2_gfx102_sw_64kb_s_t,
-       dml2_gfx102_sw_64kb_s_x,
-       dml2_gfx102_sw_64kb_r_x,
-
-       dml2_linear_64elements, // GFX7 LINEAR_ALIGNED accepts pitch alignment 
of the maximum of 64 elements or 256 bytes
-       dml2_gfx7_1d_thin,
-       dml2_gfx7_2d_thin_gen_zero,
-       dml2_gfx7_2d_thin_gen_one,
-       dml2_gfx7_2d_thin_arlene,
-       dml2_gfx7_2d_thin_anubis
 };
 
 enum dml2_source_format_class {
diff --git 
a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c 
b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
index cd9bf190cb1a..5dc846802c53 100644
--- 
a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
+++ 
b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
@@ -428,10 +428,6 @@ bool dml2_core_utils_is_phantom_pipe(const struct 
dml2_plane_parameters *plane_c
 
 unsigned int dml2_core_utils_get_tile_block_size_bytes(enum dml2_swizzle_mode 
sw_mode, unsigned int byte_per_pixel)
 {
-       if (dml2_core_utils_get_gfx_version(sw_mode) == 10 || 
dml2_core_utils_get_gfx_version(sw_mode) == 7) {
-               return 
dml2_core_utils_get_tile_block_size_bytes_backcompat(sw_mode, byte_per_pixel);
-       }
-
        if (sw_mode == dml2_sw_linear)
                return 256;
        else if (sw_mode == dml2_sw_256b_2d)
@@ -462,56 +458,14 @@ unsigned int 
dml2_core_utils_get_tile_block_size_bytes(enum dml2_swizzle_mode sw
        };
 }
 
-unsigned int dml2_core_utils_get_tile_block_size_bytes_backcompat(enum 
dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel)
-{
-       if (sw_mode == dml2_sw_linear_256b)
-               return 256;
-       else if (sw_mode == dml2_gfx10_sw_64kb_r_x)
-               return 65536;
-       else if (sw_mode == dml2_gfx102_sw_64kb_s)
-               return 65536;
-       else if (sw_mode == dml2_gfx102_sw_64kb_s_t)
-               return 65536;
-       else if (sw_mode == dml2_gfx102_sw_64kb_s_x)
-               return 65536;
-       else if (sw_mode == dml2_gfx102_sw_64kb_r_x)
-               return 65536;
-       else if (sw_mode == dml2_linear_64elements)
-               return 256;
-       else if (sw_mode == dml2_gfx7_1d_thin)
-               return 256;
-       else if (sw_mode == dml2_gfx7_2d_thin_gen_zero)
-               return (128 * 64 * byte_per_pixel);
-       else if (sw_mode == dml2_gfx7_2d_thin_gen_one)
-               return (128 * 128 * byte_per_pixel);
-       else if (sw_mode == dml2_gfx7_2d_thin_arlene)
-               return (64 * 32 * byte_per_pixel);
-       else if (sw_mode == dml2_gfx7_2d_thin_anubis)
-               return (128 * 128 * byte_per_pixel);
-       else {
-               DML_ASSERT(0);
-               return 256;
-       };
-}
-
 bool dml2_core_utils_get_segment_horizontal_contiguous(enum dml2_swizzle_mode 
sw_mode, unsigned int byte_per_pixel)
 {
-       if (dml2_core_utils_get_gfx_version(sw_mode) == 10 || 
dml2_core_utils_get_gfx_version(sw_mode) == 7) {
-               return 
dml2_core_utils_get_segment_horizontal_contiguous_backcompat(sw_mode, 
byte_per_pixel);
-       } else {
-               return (byte_per_pixel != 2);
-       }
-}
-
-bool dml2_core_utils_get_segment_horizontal_contiguous_backcompat(enum 
dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel)
-{
-       return !((byte_per_pixel == 4) &&
-               ((sw_mode == dml2_gfx10_sw_64kb_r_x) || (sw_mode == 
dml2_gfx102_sw_64kb_s) || (sw_mode == dml2_gfx102_sw_64kb_s_t) || (sw_mode == 
dml2_gfx102_sw_64kb_s_x)));
+       return (byte_per_pixel != 2);
 }
 
 bool dml2_core_utils_is_linear(enum dml2_swizzle_mode sw_mode)
 {
-       return (sw_mode == dml2_sw_linear || sw_mode == dml2_sw_linear_256b || 
sw_mode == dml2_linear_64elements);
+       return sw_mode == dml2_sw_linear;
 };
 
 
@@ -544,20 +498,6 @@ int unsigned dml2_core_utils_get_gfx_version(enum 
dml2_swizzle_mode sw_mode)
                sw_mode == dml2_gfx11_sw_256kb_d_x ||
                sw_mode == dml2_gfx11_sw_256kb_r_x)
                version = 11;
-       else if (sw_mode == dml2_sw_linear_256b ||
-               sw_mode == dml2_gfx10_sw_64kb_r_x ||
-               sw_mode == dml2_gfx102_sw_64kb_s ||
-               sw_mode == dml2_gfx102_sw_64kb_s_t ||
-               sw_mode == dml2_gfx102_sw_64kb_s_x ||
-               sw_mode == dml2_gfx102_sw_64kb_r_x)
-               version = 10;
-       else if (sw_mode == dml2_linear_64elements ||
-               sw_mode == dml2_gfx7_1d_thin ||
-               sw_mode == dml2_gfx7_2d_thin_gen_zero ||
-               sw_mode == dml2_gfx7_2d_thin_gen_one ||
-               sw_mode == dml2_gfx7_2d_thin_arlene ||
-               sw_mode == dml2_gfx7_2d_thin_anubis)
-               version = 7;
        else {
                DML_LOG_VERBOSE("ERROR: Invalid sw_mode setting! val=%u\n", 
sw_mode);
                DML_ASSERT(0);
diff --git 
a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h 
b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h
index 471e73ed671c..95f0d017add4 100644
--- 
a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h
+++ 
b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h
@@ -22,8 +22,6 @@ void dml2_core_utils_pipe_plane_mapping(const struct 
core_display_cfg_support_in
 bool dml2_core_utils_is_phantom_pipe(const struct dml2_plane_parameters 
*plane_cfg);
 unsigned int dml2_core_utils_get_tile_block_size_bytes(enum dml2_swizzle_mode 
sw_mode, unsigned int byte_per_pixel);
 bool dml2_core_utils_get_segment_horizontal_contiguous(enum dml2_swizzle_mode 
sw_mode, unsigned int byte_per_pixel);
-unsigned int dml2_core_utils_get_tile_block_size_bytes_backcompat(enum 
dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel);
-bool dml2_core_utils_get_segment_horizontal_contiguous_backcompat(enum 
dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel);
 bool dml2_core_utils_is_vertical_rotation(enum dml2_rotation_angle Scan);
 bool dml2_core_utils_is_linear(enum dml2_swizzle_mode sw_mode);
 int unsigned dml2_core_utils_get_gfx_version(enum dml2_swizzle_mode sw_mode);
-- 
2.34.1

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