On Fri, Mar 20, 2026 at 4:02 PM Amber Lin <[email protected]> wrote: > > Same as compute and sdma, gfx_hqd_mask has been initialized properly in > amdgpu_mes_init. set_hw_res should use those initialization accordingly. > Hardcoding it causes the mismatch between driver and MES. > > Signed-off-by: Amber Lin <[email protected]>
Reviewed-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/mes_v12_1.c | 15 +++------------ > 1 file changed, 3 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c > b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c > index 5dcc2c32644a..70d80c2aed52 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c > @@ -633,17 +633,6 @@ static int mes_v12_1_set_hw_resources_1(struct > amdgpu_mes *mes, > offsetof(union MESAPI_SET_HW_RESOURCES_1, > api_status)); > } > > -static void mes_v12_1_set_gfx_hqd_mask(union MESAPI_SET_HW_RESOURCES *pkt) > -{ > - /* > - * GFX V12 has only one GFX pipe, but 8 queues in it. > - * GFX pipe 0 queue 0 is being used by Kernel queue. > - * Set GFX pipe 0 queue 1-7 for MES scheduling > - * mask = 1111 1110b > - */ > - pkt->gfx_hqd_mask[0] = 0xFE; > -} > - > static int mes_v12_1_set_hw_resources(struct amdgpu_mes *mes, > int pipe, int xcc_id) > { > @@ -667,7 +656,9 @@ static int mes_v12_1_set_hw_resources(struct amdgpu_mes > *mes, > mes_set_hw_res_pkt.compute_hqd_mask[i] = > mes->compute_hqd_mask[i]; > > - mes_v12_1_set_gfx_hqd_mask(&mes_set_hw_res_pkt); > + for (i = 0; i < MAX_GFX_PIPES; i++) > + mes_set_hw_res_pkt.gfx_hqd_mask[i] = > + mes->gfx_hqd_mask[i]; > > for (i = 0; i < MAX_SDMA_PIPES; i++) > mes_set_hw_res_pkt.sdma_hqd_mask[i] = > -- > 2.43.0 >
