PCTL0__MMHUB_DEEPSLEEP_IB on MMHUB 4,1,0 is 0x69004. If deepsleep is working then the MMHUB clock will run slower while idle but speed up once anything happens, so some operations might take a little longer to get started.
Based on the logic above and tested on RX9070. 1 with 0x69004 set 0x80004000 at start, 0x4000 at end 2 with 0x69004 set 0x4000 always at start and end 3 with 0x62a04 in case 1 results: - case 1 shows the best startup performance. speed=9.8x - case 2 shows the worst startup performance. speed=7.5x - case 3 is a little bit better than case 2 at startup. speed=7.7x This clearly indicates the case 1 is correct. Signed-off-by: David (Ming Qiang) Wu <[email protected]> --- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index 4b4aa9553624..62eb98450426 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -739,7 +739,16 @@ void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring) if (!amdgpu_sriov_vf(ring->adev)) { amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 0, 0, PACKETJ_TYPE0)); - amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ + + /* PCTL0__MMHUB_DEEPSLEEP_IB could be different on different mmhub version */ + switch (amdgpu_ip_version(ring->adev, MMHUB_HWIP, 0)) { + case IP_VERSION(4, 1, 0): + amdgpu_ring_write(ring, 0x69004); + break; + default: + amdgpu_ring_write(ring, 0x62a04); + break; + } amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0, @@ -760,7 +769,16 @@ void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring) if (!amdgpu_sriov_vf(ring->adev)) { amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 0, 0, PACKETJ_TYPE0)); - amdgpu_ring_write(ring, 0x62a04); + + /* PCTL0__MMHUB_DEEPSLEEP_IB could be different on different mmhub version */ + switch (amdgpu_ip_version(ring->adev, MMHUB_HWIP, 0)) { + case IP_VERSION(4, 1, 0): + amdgpu_ring_write(ring, 0x69004); + break; + default: + amdgpu_ring_write(ring, 0x62a04); + break; + } amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0, -- 2.43.0
