From: Taimur Hassan <[email protected]> This version brings along the following updates:
- Cleanup, refactoring of panel replay code to prepare for non-eDP replay - Switch to drm_dbg_macros instead of DRM_DEBUG variants - Add pwait status to DMCUB debug logging - Adjust PHY FSM transition to TX_EN-to-PLL_ON for TMDS on DCN35 - Always update divider settings for DP tunnel - correct clip x assignment in cursor programming - Bump the HDMI clock to 340MHz Signed-off-by: Taimur Hassan <[email protected]> Signed-off-by: Matthew Stewart <[email protected]> --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 0724d92a2353..4068d5baef21 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -63,7 +63,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.364" +#define DC_VER "3.2.365" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC -- 2.52.0
