[AMD Official Use Only - AMD Internal Distribution Only] Reviewed-by: Emily Deng <[email protected]>
>-----Original Message----- >From: SHANMUGAM, SRINIVASAN <[email protected]> >Sent: Thursday, December 18, 2025 5:57 PM >To: Koenig, Christian <[email protected]>; Deucher, Alexander ><[email protected]> >Cc: [email protected]; SHANMUGAM, SRINIVASAN ><[email protected]>; Opara, Darlington ><[email protected]>; Jinage Zhao <[email protected]>; Liu, Monk ><[email protected]>; Deng, Emily <[email protected]> >Subject: [PATCH] drm/amdgpu: Use explicit VCN instance 0 in SR-IOV init > >vcn_v2_0_start_sriov() declares a local variable "i" initialized to zero and >uses it only >as the instance index in SOC15_REG_OFFSET(UVD, i, ...). >The value is never changed and all other fields are taken from >adev->vcn.inst[0], so this path only ever programs VCN instance 0. > >This triggered a Smatch: >warn: iterator 'i' not incremented > >Replace the dummy iterator with an explicit instance index of 0 in >SOC15_REG_OFFSET() calls. > >Fixes: dd26858a9cd8 ("drm/amdgpu: implement initialization part on VCN2.0 for >SRIOV") Reported by: Dan Carpenter <[email protected]> >Cc: darlington Opara <[email protected]> >Cc: Jinage Zhao <[email protected]> >Cc: Monk Liu <[email protected]> >Cc: Emily Deng <[email protected]> >Cc: Christian König <[email protected]> >Cc: Alex Deucher <[email protected]> >Signed-off-by: Srinivasan Shanmugam <[email protected]> >Change-Id: I447f68cd988561309de8da8dd4a65275bd8c99ab >--- > drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 45 ++++++++++++++------------- > 1 file changed, 23 insertions(+), 22 deletions(-) > >diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c >b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c >index 8897dcc9c1a0..e35fae9cdaf6 100644 >--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c >+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c >@@ -1964,7 +1964,8 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device >*adev) > struct mmsch_v2_0_cmd_end end = { {0} }; > struct mmsch_v2_0_init_header *header; > uint32_t *init_table = adev->virt.mm_table.cpu_addr; >- uint8_t i = 0; >+ >+ /* This path only programs VCN instance 0. */ > > header = (struct mmsch_v2_0_init_header *)init_table; > direct_wt.cmd_header.command_type = >MMSCH_COMMAND__DIRECT_REG_WRITE; @@ -1983,93 +1984,93 @@ static >int vcn_v2_0_start_sriov(struct amdgpu_device *adev) > size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4); > > MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT( >- SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), >+ SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), > 0xFFFFFFFF, 0x00000004); > > /* mc resume*/ > if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { > MMSCH_V2_0_INSERT_DIRECT_WT( >- SOC15_REG_OFFSET(UVD, i, >+ SOC15_REG_OFFSET(UVD, 0, > > mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), > adev- >>firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo); > MMSCH_V2_0_INSERT_DIRECT_WT( >- SOC15_REG_OFFSET(UVD, i, >+ SOC15_REG_OFFSET(UVD, 0, > > mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), > adev- >>firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi); > offset = 0; > } else { > MMSCH_V2_0_INSERT_DIRECT_WT( >- SOC15_REG_OFFSET(UVD, i, >+ SOC15_REG_OFFSET(UVD, 0, > > mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), > lower_32_bits(adev->vcn.inst->gpu_addr)); > MMSCH_V2_0_INSERT_DIRECT_WT( >- SOC15_REG_OFFSET(UVD, i, >+ SOC15_REG_OFFSET(UVD, 0, > > mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), > upper_32_bits(adev->vcn.inst->gpu_addr)); > offset = size; > } > > MMSCH_V2_0_INSERT_DIRECT_WT( >- SOC15_REG_OFFSET(UVD, i, >mmUVD_VCPU_CACHE_OFFSET0), >+ SOC15_REG_OFFSET(UVD, 0, >mmUVD_VCPU_CACHE_OFFSET0), > 0); > MMSCH_V2_0_INSERT_DIRECT_WT( >- SOC15_REG_OFFSET(UVD, i, >mmUVD_VCPU_CACHE_SIZE0), >+ SOC15_REG_OFFSET(UVD, 0, >mmUVD_VCPU_CACHE_SIZE0), > size); > > MMSCH_V2_0_INSERT_DIRECT_WT( >- SOC15_REG_OFFSET(UVD, i, >+ SOC15_REG_OFFSET(UVD, 0, > mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), > lower_32_bits(adev->vcn.inst->gpu_addr + offset)); > MMSCH_V2_0_INSERT_DIRECT_WT( >- SOC15_REG_OFFSET(UVD, i, >+ SOC15_REG_OFFSET(UVD, 0, > mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), > upper_32_bits(adev->vcn.inst->gpu_addr + offset)); > MMSCH_V2_0_INSERT_DIRECT_WT( >- SOC15_REG_OFFSET(UVD, i, >mmUVD_VCPU_CACHE_OFFSET1), >+ SOC15_REG_OFFSET(UVD, 0, >mmUVD_VCPU_CACHE_OFFSET1), > 0); > MMSCH_V2_0_INSERT_DIRECT_WT( >- SOC15_REG_OFFSET(UVD, i, >mmUVD_VCPU_CACHE_SIZE1), >+ SOC15_REG_OFFSET(UVD, 0, >mmUVD_VCPU_CACHE_SIZE1), > AMDGPU_VCN_STACK_SIZE); > > MMSCH_V2_0_INSERT_DIRECT_WT( >- SOC15_REG_OFFSET(UVD, i, >+ SOC15_REG_OFFSET(UVD, 0, > mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), > lower_32_bits(adev->vcn.inst->gpu_addr + offset + > AMDGPU_VCN_STACK_SIZE)); > MMSCH_V2_0_INSERT_DIRECT_WT( >- SOC15_REG_OFFSET(UVD, i, >+ SOC15_REG_OFFSET(UVD, 0, > mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), > upper_32_bits(adev->vcn.inst->gpu_addr + offset + > AMDGPU_VCN_STACK_SIZE)); > MMSCH_V2_0_INSERT_DIRECT_WT( >- SOC15_REG_OFFSET(UVD, i, >mmUVD_VCPU_CACHE_OFFSET2), >+ SOC15_REG_OFFSET(UVD, 0, >mmUVD_VCPU_CACHE_OFFSET2), > 0); > MMSCH_V2_0_INSERT_DIRECT_WT( >- SOC15_REG_OFFSET(UVD, i, >mmUVD_VCPU_CACHE_SIZE2), >+ SOC15_REG_OFFSET(UVD, 0, >mmUVD_VCPU_CACHE_SIZE2), > AMDGPU_VCN_CONTEXT_SIZE); > > for (r = 0; r < adev->vcn.inst[0].num_enc_rings; ++r) { > ring = &adev->vcn.inst->ring_enc[r]; > ring->wptr = 0; > MMSCH_V2_0_INSERT_DIRECT_WT( >- SOC15_REG_OFFSET(UVD, i, >mmUVD_RB_BASE_LO), >+ SOC15_REG_OFFSET(UVD, 0, >mmUVD_RB_BASE_LO), > lower_32_bits(ring->gpu_addr)); > MMSCH_V2_0_INSERT_DIRECT_WT( >- SOC15_REG_OFFSET(UVD, i, >mmUVD_RB_BASE_HI), >+ SOC15_REG_OFFSET(UVD, 0, >mmUVD_RB_BASE_HI), > upper_32_bits(ring->gpu_addr)); > MMSCH_V2_0_INSERT_DIRECT_WT( >- SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), >+ SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE), > ring->ring_size / 4); > } > > ring = &adev->vcn.inst->ring_dec; > ring->wptr = 0; > MMSCH_V2_0_INSERT_DIRECT_WT( >- SOC15_REG_OFFSET(UVD, i, >+ SOC15_REG_OFFSET(UVD, 0, > mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), > lower_32_bits(ring->gpu_addr)); > MMSCH_V2_0_INSERT_DIRECT_WT( >- SOC15_REG_OFFSET(UVD, i, >+ SOC15_REG_OFFSET(UVD, 0, > mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), > upper_32_bits(ring->gpu_addr)); > /* force RBC into idle state */ >@@ -2080,7 +2081,7 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device >*adev) > tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, >RB_NO_UPDATE, 1); > tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, >RB_RPTR_WR_EN, 1); > MMSCH_V2_0_INSERT_DIRECT_WT( >- SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), >tmp); >+ SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), >tmp); > > /* add end packet */ > tmp = sizeof(struct mmsch_v2_0_cmd_end); >-- >2.34.1
