Hello Monk Liu,
Commit dd26858a9cd8 ("drm/amdgpu: implement initialization part on
VCN2.0 for SRIOV") from Mar 5, 2020 (linux-next), leads to the
following Smatch static checker warning:
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1967 vcn_v2_0_start_sriov()
warn: iterator 'i' not incremented
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1955 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
1956 {
1957 int r;
1958 uint32_t tmp;
1959 struct amdgpu_ring *ring;
1960 uint32_t offset, size;
1961 uint32_t table_size = 0;
1962 struct mmsch_v2_0_cmd_direct_write direct_wt = { {0} };
1963 struct mmsch_v2_0_cmd_direct_read_modify_write direct_rd_mod_wt
= { {0} };
1964 struct mmsch_v2_0_cmd_end end = { {0} };
1965 struct mmsch_v2_0_init_header *header;
1966 uint32_t *init_table = adev->virt.mm_table.cpu_addr;
1967 uint8_t i = 0;
i is always just zero. What's the dealio, yo?
1968
1969 header = (struct mmsch_v2_0_init_header *)init_table;
1970 direct_wt.cmd_header.command_type =
MMSCH_COMMAND__DIRECT_REG_WRITE;
1971 direct_rd_mod_wt.cmd_header.command_type =
1972 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1973 end.cmd_header.command_type = MMSCH_COMMAND__END;
1974
1975 if (header->vcn_table_offset == 0 && header->vcn_table_size ==
0) {
1976 header->version = MMSCH_VERSION;
1977 header->header_size = sizeof(struct
mmsch_v2_0_init_header) >> 2;
1978
1979 header->vcn_table_offset = header->header_size;
1980
1981 init_table += header->vcn_table_offset;
1982
1983 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size
+ 4);
1984
1985 MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(
1986 SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
1987 0xFFFFFFFF, 0x00000004);
1988
1989 /* mc resume*/
1990 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1991 MMSCH_V2_0_INSERT_DIRECT_WT(
1992 SOC15_REG_OFFSET(UVD, i,
1993
mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1994
adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo);
1995 MMSCH_V2_0_INSERT_DIRECT_WT(
1996 SOC15_REG_OFFSET(UVD, i,
1997
mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1998
adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi);
1999 offset = 0;
2000 } else {
2001 MMSCH_V2_0_INSERT_DIRECT_WT(
2002 SOC15_REG_OFFSET(UVD, i,
2003
mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
2004
lower_32_bits(adev->vcn.inst->gpu_addr));
2005 MMSCH_V2_0_INSERT_DIRECT_WT(
2006 SOC15_REG_OFFSET(UVD, i,
2007
mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
2008
upper_32_bits(adev->vcn.inst->gpu_addr));
2009 offset = size;
2010 }
2011
2012 MMSCH_V2_0_INSERT_DIRECT_WT(
2013 SOC15_REG_OFFSET(UVD, i,
mmUVD_VCPU_CACHE_OFFSET0),
2014 0);
2015 MMSCH_V2_0_INSERT_DIRECT_WT(
2016 SOC15_REG_OFFSET(UVD, i,
mmUVD_VCPU_CACHE_SIZE0),
2017 size);
2018
2019 MMSCH_V2_0_INSERT_DIRECT_WT(
2020 SOC15_REG_OFFSET(UVD, i,
2021 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
2022 lower_32_bits(adev->vcn.inst->gpu_addr +
offset));
2023 MMSCH_V2_0_INSERT_DIRECT_WT(
2024 SOC15_REG_OFFSET(UVD, i,
2025 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
2026 upper_32_bits(adev->vcn.inst->gpu_addr +
offset));
2027 MMSCH_V2_0_INSERT_DIRECT_WT(
2028 SOC15_REG_OFFSET(UVD, i,
mmUVD_VCPU_CACHE_OFFSET1),
2029 0);
2030 MMSCH_V2_0_INSERT_DIRECT_WT(
2031 SOC15_REG_OFFSET(UVD, i,
mmUVD_VCPU_CACHE_SIZE1),
2032 AMDGPU_VCN_STACK_SIZE);
2033
2034 MMSCH_V2_0_INSERT_DIRECT_WT(
2035 SOC15_REG_OFFSET(UVD, i,
2036 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
2037 lower_32_bits(adev->vcn.inst->gpu_addr + offset
+
2038 AMDGPU_VCN_STACK_SIZE));
2039 MMSCH_V2_0_INSERT_DIRECT_WT(
2040 SOC15_REG_OFFSET(UVD, i,
2041 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
2042 upper_32_bits(adev->vcn.inst->gpu_addr + offset
+
2043 AMDGPU_VCN_STACK_SIZE));
2044 MMSCH_V2_0_INSERT_DIRECT_WT(
2045 SOC15_REG_OFFSET(UVD, i,
mmUVD_VCPU_CACHE_OFFSET2),
2046 0);
2047 MMSCH_V2_0_INSERT_DIRECT_WT(
2048 SOC15_REG_OFFSET(UVD, i,
mmUVD_VCPU_CACHE_SIZE2),
2049 AMDGPU_VCN_CONTEXT_SIZE);
2050
2051 for (r = 0; r < adev->vcn.inst[0].num_enc_rings; ++r) {
2052 ring = &adev->vcn.inst->ring_enc[r];
2053 ring->wptr = 0;
2054 MMSCH_V2_0_INSERT_DIRECT_WT(
2055 SOC15_REG_OFFSET(UVD, i,
mmUVD_RB_BASE_LO),
2056 lower_32_bits(ring->gpu_addr));
2057 MMSCH_V2_0_INSERT_DIRECT_WT(
2058 SOC15_REG_OFFSET(UVD, i,
mmUVD_RB_BASE_HI),
2059 upper_32_bits(ring->gpu_addr));
2060 MMSCH_V2_0_INSERT_DIRECT_WT(
2061 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE),
2062 ring->ring_size / 4);
2063 }
2064
2065 ring = &adev->vcn.inst->ring_dec;
2066 ring->wptr = 0;
2067 MMSCH_V2_0_INSERT_DIRECT_WT(
2068 SOC15_REG_OFFSET(UVD, i,
2069 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
2070 lower_32_bits(ring->gpu_addr));
2071 MMSCH_V2_0_INSERT_DIRECT_WT(
2072 SOC15_REG_OFFSET(UVD, i,
2073 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
2074 upper_32_bits(ring->gpu_addr));
2075 /* force RBC into idle state */
2076 tmp = order_base_2(ring->ring_size);
2077 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
2078 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
2079 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH,
1);
2080 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE,
1);
2081 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL,
RB_RPTR_WR_EN, 1);
2082 MMSCH_V2_0_INSERT_DIRECT_WT(
2083 SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL),
tmp);
2084
2085 /* add end packet */
2086 tmp = sizeof(struct mmsch_v2_0_cmd_end);
2087 memcpy((void *)init_table, &end, tmp);
2088 table_size += (tmp / 4);
2089 header->vcn_table_size = table_size;
2090
2091 }
2092 return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table);
2093 }
regards,
dan carpenter
