> GFX ring resets work differently on pre-GFX10 hardware since > > there is no MQD managed by the scheduler. > > For ring reset, you need issue the reset via CP_VMID_RESET > > via KIQ or MMIO and submit the following to the gfx ring to > > complete the reset: > > 1. EOP packet with EXEC bit set > > 2. WAIT_REG_MEM to wait for the fence > > 3. Clear CP_VMID_RESET to 0 > > 4. EVENT_WRITE ENABLE_LEGACY_PIPELINE > > 5. EOP packet with EXEC bit set > > 6. WAIT_REG_MEM to wait for the fence > > Once those commands have completed the reset should > > be complete and the ring can accept new packets. > > > > However, because we have a pipeline sync between jobs, > > the PFP is waiting on the fence from the bad job to signal so > > it can't process any of the packets in the reset sequence > > until that pipeline sync clears. To unblock the PFP, we > > use the KIQ to signal the fence after we reset the queue. > > > > Signed-off-by: Alex Deucher <[email protected]> > > --- > > Tested-by: Jiqian Chen <[email protected]>
> > -- Best regards, Jiqian Chen.
