From: Kaier Hsueg <[email protected]> [WHY] When performing 4:1 downscaling with subsampled formats, the SPL remainder distribution logic (+1) overrides the upper layer’s aligned width, resulting in odd segment widths and causing hang.
The upper layer alignment ensures the width is sufficient and even, so SPL should not modify it further. [HOW] In dc_spl.c within calculate_mpc_slice_in_timing_active, add an extra condition: Skip the remainder distribution (+1) when use_recout_width_aligned is true.This change respects the upper layer’s alignment decision, prevents odd widths, and is a minimal, safe fix. Reviewed-by: Joshua Aberback <[email protected]> Signed-off-by: Kaier Hsueh <[email protected]> Signed-off-by: Chenyu Chen <[email protected]> --- drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c index f506ab70a307..d8aebaff7c3f 100644 --- a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c +++ b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c @@ -226,7 +226,8 @@ static struct spl_rect calculate_mpc_slice_in_timing_active( /* extra pixels in the division remainder need to go to pipes after * the extra pixel index minus one(epimo) defined here as: */ - if (mpc_slice_idx > epimo && spl_in->basic_in.custom_width == 0) { + if ((use_recout_width_aligned == false) && + mpc_slice_idx > epimo && spl_in->basic_in.custom_width == 0) { mpc_rec.x += mpc_slice_idx - epimo - 1; mpc_rec.width += 1; } -- 2.43.0
